cortex_a: Rename APB-AP to CPU in memory contexts

Memory accesses are not made through the APB-AP, they are made through
the CPU (which happens to be controlled over the APB-AP). Rename all
irrelevant uses of the APB-AP term. And fix the long standing typo in
the function names...

Change-Id: Ide466fb2728930968bdba698f0dd9012cc9dbdf9
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3216
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>

1 files changed, 28 insertions, 29 deletions

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index f9ffccd0..a97e594e 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -76,7 +76,7 @@ static int cortex_a_mmu(struct target *target, int *enabled);
 static int cortex_a_mmu_modify(struct target *target, int enable);
 static int cortex_a_virt2phys(struct target *target,
 	uint32_t virt, uint32_t *phys);
-static int cortex_a_read_apb_ab_memory(struct target *target,
+static int cortex_a_read_cpu_memory(struct target *target,
 	uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 
 
@@ -2127,13 +2127,13 @@ static int cortex_a_dfsr_to_error_code(uint32_t dfsr)
 	}
 }
 
-static int cortex_a_write_apb_ab_memory_slow(struct target *target,
+static int cortex_a_write_cpu_memory_slow(struct target *target,
 	uint32_t size, uint32_t count, const uint8_t *buffer, uint32_t *dscr)
 {
 	/* Writes count objects of size size from *buffer. Old value of DSCR must
 	 * be in *dscr; updated to new value. This is slow because it works for
 	 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
-	 * the address is aligned, cortex_a_write_apb_ab_memory_fast should be
+	 * the address is aligned, cortex_a_write_cpu_memory_fast should be
 	 * preferred.
 	 * Preconditions:
 	 * - Address is in R0.
@@ -2202,7 +2202,7 @@ static int cortex_a_write_apb_ab_memory_slow(struct target *target,
 	return ERROR_OK;
 }
 
-static int cortex_a_write_apb_ab_memory_fast(struct target *target,
+static int cortex_a_write_cpu_memory_fast(struct target *target,
 	uint32_t count, const uint8_t *buffer, uint32_t *dscr)
 {
 	/* Writes count objects of size 4 from *buffer. Old value of DSCR must be
@@ -2231,17 +2231,17 @@ static int cortex_a_write_apb_ab_memory_fast(struct target *target,
 			4, count, armv7a->debug_base + CPUDBG_DTRRX);
 }
 
-static int cortex_a_write_apb_ab_memory(struct target *target,
+static int cortex_a_write_cpu_memory(struct target *target,
 	uint32_t address, uint32_t size,
 	uint32_t count, const uint8_t *buffer)
 {
-	/* Write memory through APB-AP. */
+	/* Write memory through the CPU. */
 	int retval, final_retval;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm *arm = &armv7a->arm;
 	uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
 
-	LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx32 " size %"  PRIu32 " count %"  PRIu32,
+	LOG_DEBUG("Writing CPU memory address 0x%" PRIx32 " size %"  PRIu32 " count %"  PRIu32,
 			  address, size, count);
 	if (target->state != TARGET_HALTED) {
 		LOG_WARNING("target not halted");
@@ -2287,10 +2287,10 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
 
 	if (size == 4 && (address % 4) == 0) {
 		/* We are doing a word-aligned transfer, so use fast mode. */
-		retval = cortex_a_write_apb_ab_memory_fast(target, count, buffer, &dscr);
+		retval = cortex_a_write_cpu_memory_fast(target, count, buffer, &dscr);
 	} else {
 		/* Use slow path. */
-		retval = cortex_a_write_apb_ab_memory_slow(target, size, count, buffer, &dscr);
+		retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr);
 	}
 
 out:
@@ -2370,13 +2370,13 @@ out:
 	return final_retval;
 }
 
-static int cortex_a_read_apb_ab_memory_slow(struct target *target,
+static int cortex_a_read_cpu_memory_slow(struct target *target,
 	uint32_t size, uint32_t count, uint8_t *buffer, uint32_t *dscr)
 {
 	/* Reads count objects of size size into *buffer. Old value of DSCR must be
 	 * in *dscr; updated to new value. This is slow because it works for
 	 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
-	 * the address is aligned, cortex_a_read_apb_ab_memory_fast should be
+	 * the address is aligned, cortex_a_read_cpu_memory_fast should be
 	 * preferred.
 	 * Preconditions:
 	 * - Address is in R0.
@@ -2446,7 +2446,7 @@ static int cortex_a_read_apb_ab_memory_slow(struct target *target,
 	return ERROR_OK;
 }
 
-static int cortex_a_read_apb_ab_memory_fast(struct target *target,
+static int cortex_a_read_cpu_memory_fast(struct target *target,
 	uint32_t count, uint8_t *buffer, uint32_t *dscr)
 {
 	/* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
@@ -2533,17 +2533,17 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
 	return ERROR_OK;
 }
 
-static int cortex_a_read_apb_ab_memory(struct target *target,
+static int cortex_a_read_cpu_memory(struct target *target,
 	uint32_t address, uint32_t size,
 	uint32_t count, uint8_t *buffer)
 {
-	/* Read memory through APB-AP. */
+	/* Read memory through the CPU. */
 	int retval, final_retval;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm *arm = &armv7a->arm;
 	uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
 
-	LOG_DEBUG("Reading APB-AP memory address 0x%" PRIx32 " size %"  PRIu32 " count %"  PRIu32,
+	LOG_DEBUG("Reading CPU memory address 0x%" PRIx32 " size %"  PRIu32 " count %"  PRIu32,
 			  address, size, count);
 	if (target->state != TARGET_HALTED) {
 		LOG_WARNING("target not halted");
@@ -2589,10 +2589,10 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
 
 	if (size == 4 && (address % 4) == 0) {
 		/* We are doing a word-aligned transfer, so use fast mode. */
-		retval = cortex_a_read_apb_ab_memory_fast(target, count, buffer, &dscr);
+		retval = cortex_a_read_cpu_memory_fast(target, count, buffer, &dscr);
 	} else {
 		/* Use slow path. */
-		retval = cortex_a_read_apb_ab_memory_slow(target, size, count, buffer, &dscr);
+		retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr);
 	}
 
 out:
@@ -2686,9 +2686,9 @@ static int cortex_a_read_phys_memory(struct target *target,
 	if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap->ap_num))
 		return mem_ap_read_buf(armv7a->memory_ap, buffer, size, count, address);
 
-	/* read memory through APB-AP */
+	/* read memory through the CPU */
 	cortex_a_prep_memaccess(target, 1);
-	retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
+	retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
 	cortex_a_post_memaccess(target, 1);
 
 	return retval;
@@ -2704,7 +2704,7 @@ static int cortex_a_read_memory(struct target *target, uint32_t address,
 		size, count);
 
 	cortex_a_prep_memaccess(target, 0);
-	retval = cortex_a_read_apb_ab_memory(target, address, size, count, buffer);
+	retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
 	cortex_a_post_memaccess(target, 0);
 
 	return retval;
@@ -2771,9 +2771,9 @@ static int cortex_a_write_phys_memory(struct target *target,
 	if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap->ap_num))
 		return mem_ap_write_buf(armv7a->memory_ap, buffer, size, count, address);
 
-	/* write memory through APB-AP */
+	/* write memory through the CPU */
 	cortex_a_prep_memaccess(target, 1);
-	retval = cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
+	retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
 	cortex_a_post_memaccess(target, 1);
 
 	return retval;
@@ -2792,7 +2792,7 @@ static int cortex_a_write_memory(struct target *target, uint32_t address,
 	armv7a_cache_auto_flush_on_write(target, address, size * count);
 
 	cortex_a_prep_memaccess(target, 0);
-	retval = cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
+	retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
 	cortex_a_post_memaccess(target, 0);
 	return retval;
 }
@@ -2965,7 +2965,7 @@ static int cortex_a_examine_first(struct target *target)
 		return retval;
 	}
 
-	/* Search for the APB-AB - it is needed for access to debug registers */
+	/* Search for the APB-AP - it is needed for access to debug registers */
 	retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
 	if (retval != ERROR_OK) {
 		LOG_ERROR("Could not find APB-AP for debug access");
@@ -2989,11 +2989,10 @@ static int cortex_a_examine_first(struct target *target)
 		retval = mem_ap_init(armv7a->memory_ap);
 		if (retval == ERROR_OK)
 			armv7a->memory_ap_available = true;
-		else
-			LOG_WARNING("Could not initialize AHB-AP for memory access - using APB-AP");
-	} else {
-		/* AHB-AP not found - use APB-AP */
-		LOG_DEBUG("Could not find AHB-AP - using APB-AP for memory access");
+	}
+	if (retval != ERROR_OK) {
+		/* AHB-AP not found or unavailable - use the CPU */
+		LOG_DEBUG("No AHB-AP available for memory access");
 	}
 
 	if (!target->dbgbase_set) {