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<title>OpenOCD/tcl, branch mips-hack</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>https://git.amat.us/openocd/atom/tcl?h=mips-hack</id>
<link rel='self' href='https://git.amat.us/openocd/atom/tcl?h=mips-hack'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/openocd/'/>
<updated>2015-11-26T12:17:25Z</updated>
<entry>
<title>niietcm4: support for NIIET's Cortex-M4 microcontrollers</title>
<updated>2015-11-26T12:17:25Z</updated>
<author>
<name>Bogdan Kolbov</name>
<email>kolbov@niiet.ru</email>
</author>
<published>2015-10-13T06:19:25Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/openocd/commit/?id=ae2142d5a220a0e8eec3bceb499782ce53596f35'/>
<id>urn:sha1:ae2142d5a220a0e8eec3bceb499782ce53596f35</id>
<content type='text'>
This adds docs, example config, flash driver.
Driver is only supports K1921VK01T model for now.

Change-Id: I135259bb055dd2df1a17de99f066e2b24eae1b0f
Signed-off-by: Bogdan Kolbov &lt;kolbov@niiet.ru&gt;
Reviewed-on: http://openocd.zylin.com/3011
Tested-by: jenkins
Reviewed-by: Freddie Chopin &lt;freddie.chopin@gmail.com&gt;
</content>
</entry>
<entry>
<title>tcl/target: Add Nordic nRF52 config</title>
<updated>2015-11-20T18:28:40Z</updated>
<author>
<name>Andreas Färber</name>
<email>afaerber@suse.de</email>
</author>
<published>2015-11-17T10:59:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/openocd/commit/?id=2594c23d780863a8ab3d213217085eae66ab2be3'/>
<id>urn:sha1:2594c23d780863a8ab3d213217085eae66ab2be3</id>
<content type='text'>
Base config without flash support for now.

Change-Id: I96a5b6ad35e00dc706177ea9dbdffc384ae7f62b
Signed-off-by: Andreas Färber &lt;afaerber@suse.de&gt;
Reviewed-on: http://openocd.zylin.com/3110
Tested-by: jenkins
Reviewed-by: Spencer Oliver &lt;spen@spen-soft.co.uk&gt;
</content>
</entry>
<entry>
<title>tcl/board: Remove pflash.0 bank from twr-k60n512.cfg</title>
<updated>2015-11-20T18:27:54Z</updated>
<author>
<name>Jonathan Larmour</name>
<email>jifl@eCosCentric.com</email>
</author>
<published>2015-11-16T12:18:19Z</published>
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<id>urn:sha1:7f93aabd61702629e3fde37c5660233168f2640e</id>
<content type='text'>
The pflash.0 bank should not be present as it overlaps with
the flash bank created by target/kx.cfg, triggering an error.
This is also in line with the existing twr-k60f120m.cfg.

Change-Id: I5f620e01319d967f12e029fb6865ccdd031713b3
Signed-off-by: Jonathan Larmour &lt;jifl@eCosCentric.com&gt;
Reviewed-on: http://openocd.zylin.com/3108
Tested-by: jenkins
Reviewed-by: Tomas Vanek &lt;vanekt@fbl.cz&gt;
</content>
</entry>
<entry>
<title>at91samd: handle reset run/halt in DSU</title>
<updated>2015-11-20T18:26:05Z</updated>
<author>
<name>Tomas Vanek</name>
<email>vanekt@fbl.cz</email>
</author>
<published>2015-05-15T09:14:11Z</published>
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<id>urn:sha1:751e2454bf076708d3e695833c4def460ab41d8b</id>
<content type='text'>
Atmel introduced a "Device Service Unit" (DSU) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Function is similar to SMAP in ATSAM4L, see http://openocd.zylin.com/2604

Atmel's EDBG adapter handles DSU reset correctly without this change.

An ordinary SWD adapter leaves TCK in its default state, low.
So without this change any use of sysresetreq or srst
locks the chip in reset state until power is cycled.

A new function dsu_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and DSU reset is released then.

Additionally SWD clock comment is fixed in at91samdXX.cfg and clock is
lowered a bit to ensure a margin for RC oscillator frequency deviation.
adapter_nsrst_delay 100 is commented out because is no more necessary after
http://openocd.zylin.com/2601

Change-Id: I42e99b1b245f766616c0a0d939f60612c29bd16c
Signed-off-by: Tomas Vanek &lt;vanekt@fbl.cz&gt;
Reviewed-on: http://openocd.zylin.com/2778
Tested-by: jenkins
Reviewed-by: Spencer Oliver &lt;spen@spen-soft.co.uk&gt;
</content>
</entry>
<entry>
<title>tcl/interface/ftdi: add 100ask's OpenJTAG config</title>
<updated>2015-11-16T16:17:18Z</updated>
<author>
<name>Paul Fertser</name>
<email>fercerpav@gmail.com</email>
</author>
<published>2015-04-14T14:20:50Z</published>
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<id>urn:sha1:64802b79391c71474fd7f0a1d9d6c654fb959300</id>
<content type='text'>
Schematics provided by Matthias Bock.

Change-Id: I3d00453fece3b4df58a53bee21fff646a8b71a34
Signed-off-by: Paul Fertser &lt;fercerpav@gmail.com&gt;
Reviewed-on: http://openocd.zylin.com/2718
Tested-by: jenkins
</content>
</entry>
<entry>
<title>board: ti_am437x_idk: default to 1000kHz</title>
<updated>2015-11-13T06:59:12Z</updated>
<author>
<name>Felipe Balbi</name>
<email>balbi@ti.com</email>
</author>
<published>2015-10-13T17:26:04Z</published>
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<id>urn:sha1:e4848fe0437e32025c4749ee17bdae7cb6b2cd70</id>
<content type='text'>
16000kHz is only safe after PLLs have been locked
properly. Until that's done (with reset init), we
can only safely run at 1000kHz.

Change-Id: I4e0a17e88aa9919cd6c34d44da68e23115c0d3a3
Signed-off-by: Felipe Balbi &lt;balbi@ti.com&gt;
Reviewed-on: http://openocd.zylin.com/3015
Tested-by: jenkins
Reviewed-by: Freddie Chopin &lt;freddie.chopin@gmail.com&gt;
</content>
</entry>
<entry>
<title>topic: Interface config file for FTDI UM232H module</title>
<updated>2015-11-13T06:57:58Z</updated>
<author>
<name>Ragnar Sundblad</name>
<email>raggesu@gmail.com</email>
</author>
<published>2015-10-17T22:48:12Z</published>
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<id>urn:sha1:dd70e57b82d1ce6da45adb5958e4452a202ba666</id>
<content type='text'>
Added interface config file for the FTDI FT232H based UM232H module.
This should work with UM232H-B too, an even cheaper module, but
that has not been tested.

Change-Id: Ifc312d6741da0b7862fe07d854023190d7afe251
Signed-off-by: Ragnar Sundblad &lt;raggesu@gmail.com&gt;
Reviewed-on: http://openocd.zylin.com/3031
Tested-by: jenkins
Reviewed-by: Freddie Chopin &lt;freddie.chopin@gmail.com&gt;
</content>
</entry>
<entry>
<title>stm32l4: Add cpu and stm32l4discovery board configuration.</title>
<updated>2015-11-12T20:21:06Z</updated>
<author>
<name>Uwe Bonnes</name>
<email>bon@elektron.ikp.physik.tu-darmstadt.de</email>
</author>
<published>2015-08-23T13:04:31Z</published>
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<id>urn:sha1:f3be0f60713dcfdc122406c95b7ed330cd7b8a3e</id>
<content type='text'>
Change-Id: I20d3fcee04516eb3b9bb22933e7e366eed0c0b2e
Signed-off-by: Karl Palsson &lt;karlp@tweak.net.au&gt;
Signed-off-by: Uwe Bonnes &lt;bon@elektron.ikp.physik.tu-darmstadt.de&gt;
Reviewed-on: http://openocd.zylin.com/2942
Tested-by: jenkins
Reviewed-by: Freddie Chopin &lt;freddie.chopin@gmail.com&gt;
</content>
</entry>
<entry>
<title>tcl: Add default hooks for STM32F0x</title>
<updated>2015-11-12T20:20:33Z</updated>
<author>
<name>Uwe Bonnes</name>
<email>bon@elektron.ikp.physik.tu-darmstadt.de</email>
</author>
<published>2015-04-09T16:01:35Z</published>
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<id>urn:sha1:6b32fe4124ddcd5afc5612013c0e14c53842e750</id>
<content type='text'>
Keep clocks running in low power modes. Stop watchdogs from interfering
with the debug session. Set up PLL and increase clock at reset init.

Change-Id: I232d769d893d54e4ea9411c46c56b19587b69919
Signed-off-by: Uwe Bonnes &lt;bon@elektron.ikp.physik.tu-darmstadt.de&gt;
Reviewed-on: http://openocd.zylin.com/2707
Tested-by: jenkins
Reviewed-by: Freddie Chopin &lt;freddie.chopin@gmail.com&gt;
</content>
</entry>
<entry>
<title>tcl: Add default hooks for STM32F4x</title>
<updated>2015-11-12T15:24:19Z</updated>
<author>
<name>Uwe Bonnes</name>
<email>bon@elektron.ikp.physik.tu-darmstadt.de</email>
</author>
<published>2015-01-09T09:53:30Z</published>
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<id>urn:sha1:d8ac9d5ac559aa6aaf6ef8cf6f704c6e6b75da3a</id>
<content type='text'>
Set up PLL and increase clock at reset init.

Change-Id: I611bc6fb7c0c5afd8ed3f4ad8e64f3c7b981d31c
Signed-off-by: Uwe Bonnes &lt;bon@elektron.ikp.physik.tu-darmstadt.de&gt;
Reviewed-on: http://openocd.zylin.com/2609
Tested-by: jenkins
Reviewed-by: Rémi PRUD'HOMME &lt;prudhomme.remi@gmail.com&gt;
Reviewed-by: Freddie Chopin &lt;freddie.chopin@gmail.com&gt;
</content>
</entry>
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