OpenOCD/src, branch mips-hack

Some hack for MIPS, don't remember the details

2017-09-15T19:42:14Z

cortex_a: fix fast-mode memory reads

2015-12-01T06:52:01Z

cortex_a_read_apb_ab_memory_fast() uses the wrong order of ITR and DSCR writes when setting up the transfer. ARM DDI0406C says in C8.2 regarding "Fast mode" operation to first switch to fast mode and then latch the instruction in ITR. Current implementation first wrote ITR, causing the instruction to be executed immediately, then switched to fast mode without an instruction latched. Repeated reading of DTRTX didn't execute LDC and thus replicated its current content into the whole buffer. This patch uses the following, revised algorithm: 1) switch to non-blocking mode and issue the LDC for the first word 2) if more than one word is to be read: - switch to fast mode - latch the LDC instruction into ITR (it is _not_ executed) - issue (count-1) reads of DTRTX register, each read returns the current content of DTRTX and re-issues the latched instruction -> now the second-to-last word is in the buffer and the LDC for the last word has been issued. 3) wait for the last instruction to complete 4) switch back to non-blocking mode 5) Read DTRTX for the last (or: only) word and put it into the buffer Change-Id: I44f5c585962ffa5af257c3d5a2a802c122b6b1e4 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3122 Tested-by: jenkins Reviewed-by: Christopher Head Reviewed-by: Paul Fertser

xsvf: output a warning suggesting using SVF

2015-11-30T10:11:16Z

Change-Id: Iff13019aa96c528268a2be029b4acd65a00a598e Signed-off-by: Paul Fertser Reviewed-on: http://openocd.zylin.com/2907 Tested-by: jenkins

cortex_a: replace cortex_a_check_address function

2015-11-30T10:07:54Z

When accessing memory through the ARM core, privilege levels and mmu access permissions observed. Thus it depends on the current mode of the ARM core whether an access is possible or not. the ARM in USR mode can not access memory mapped to a higher privilege level. This means, if the ARM core is halted while executing at PL0, the debugger would be prevented from setting a breakpoint at an address with a higher privilege level, e.g. in the OS kernel. This is not desirable. cortex_a_check_address() tried to work around this by predicting if an access would fail and switched the ARM core to SVC mode. However, the prediction was based on hardcoded address ranges and only worked for Linux and a 3G/1G user/kernel space split. This patch changes the policy to always switch to SVC mode for memory accesses. It introduces two functions cortex_a_prep_memaccess() and cortex_a_post_memaccess() which bracket memory reads and writes. These function encapsulate all actions necessary for preparation and cleanup. Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3119 Reviewed-by: Paul Fertser Tested-by: jenkins

cortex_a: rework mmu manipulation

2015-11-30T10:07:33Z

when disabling the mmu to access physical addresses, normally the d-cache must be disabled as well. Disabling the d-cache also requires a full clean&invalidate. However, since all memory writes are treated as write- through no-allocate and memory reads do not allocate cache lines, effectively the d-cache state does not change at all. We can therefore save the the d-cache disabling and flushing. This patch also simplifies the function a bit. Change-Id: Ia17c56a28f432156429cd4596107e3652b788e63 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3114 Tested-by: jenkins Reviewed-by: Paul Fertser

cortex_a: force cache and tlb bypass when cpu is in debug state

2015-11-30T10:07:10Z

for minimal impact on the hardware state, force all memory accesses to bypass the caches and tlbs. This may actually be the default, but ARM recommends in DDI0406C to set proper default values on debug init. Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3079 Reviewed-by: Paul Fertser Tested-by: jenkins

armv7a: fix-up dcache clean and flush functions inner loop pattern

2015-11-30T05:43:42Z

Other cache functions use an updated pattern for the address range loop. Bring dcache clean and flush functions in line. Change-Id: Iccb4a05c49054471033a3403363110cb08245d5b Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3035 Tested-by: jenkins Reviewed-by: Paul Fertser

cortex_a: Update instruction cache after setting a soft breakpoint

2015-11-30T05:43:03Z

Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint, to make sure the d-cache is clean and invalid at the breakpoint location down to PoC. Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint again, so that d-cache will pick up the modified code. Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint to memory to make the change visible to the CPU. Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3033 Reviewed-by: Paul Fertser Tested-by: jenkins

armv7a: correctly handle invalidation of inner data caches

2015-11-30T05:42:35Z

D-Cache invalidate is a dangerous operation. It will only work correctly if full cache lines are invalidated. When partial cache lines are invalidated, i.e. the target address range does not start and end at a cache line boundary, cpu data writes outside of the target range will be dropped. This patch adds special treatment for partial cache lines by doing a clean & invalidate on the partial lines before invalidating the rest of the range. Change-Id: I64099ddb058638e990a7eb0ee911b9cc8f6f8901 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3034 Tested-by: jenkins Reviewed-by: Paul Fertser

armv7a: fix debug messages regarding cache on/off state

2015-11-30T05:42:13Z

Cache bits are not level specific, remove "l1" from debug message. Also, fix data/instruction mixup in armv7a_l1_i_cache_sanity_check() Change-Id: I259665ffe62c7ada5b4f98d3fd907e93662d4091 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3028 Reviewed-by: Paul Fertser Tested-by: jenkins