OpenOCD/src/target, branch master

target/cortex_a: add hypervisor mode

2020-03-12T10:11:19Z

Hypervisor mode is present only if the optional virtualization extensions are available. Moreover, virtualization extensions require that also security extensions are implemented. Add the required infrastructure for the shadowed registers in hypervisor mode. Make monitor shadowed registers visible in hypervisor mode too. Make hypervisor shadowed registers visible in hypervisor mode only. Check during cortex_a examine if virtualization extensions are present and then conditionally enable the visibility of both hypervisor and monitor modes shadowed registers. Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5261 Tested-by: jenkins

armv7a: access monitor registers only with security extensions

2020-03-12T10:10:33Z

Accordingly to ARM DDI 0406C at B1.5, the security extensions for armv7a are optional extensions and can be detected by reading ID_PFR1. The monitor mode is part of the security extensions and the shadow registers "sp_mon", "lr_mon" and "spsr_mon" are only present with the security extensions. Read the register ID_PFR1 during cortex_a examine, determine if security extension is present and then conditionally enable the visibility of the monitor mode shadow registers. Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5259 Tested-by: jenkins

target/armv4_5: remove unused macro

2020-03-12T10:09:15Z

The macro ARMV4_5_CORE_REG_MODENUM() is unused. Remove it! Change-Id: I183df57bd86c9428710ea3583e43fba88fd26e0a Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5260 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid

arm: Use different enum for core_type and core_mode

2020-03-12T10:05:42Z

The fields core_type and core_mode use the same enum arm_mode but encode different information, making the code less immediate to read. Use a different enum arm_core_type for the field core_type. The code behavior is not changed. Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5258 Tested-by: jenkins

arm: fix reg num for Monitor mode

2020-03-12T10:05:30Z

Commit 2efb1f14f611 ("Add GDB remote target description support for ARM4") inserts two additional registers "sp" and "lr" in the table arm_core_regs[], thus shifting by two the position of the last three registers already present "sp_mon" moved from index 37 to 39 "lr_mon" moved from index 38 to 40 "spsr_mon" moved from index 39 to 41 Part of the code is updated (e.g. enum defining ARM_SPSR_MON and array arm_mon_indices[]), but it's missing the update of mapping in armv4_5_core_reg_map[]. Fix armv4_5_core_reg_map[]. Change-Id: I0bdf766183392eb738206b876cd9559aacc29fa0 Signed-off-by: Antonio Borneo Fixes: 2efb1f14f611 ("Add GDB remote target description support for ARM4") Reviewed-on: http://openocd.zylin.com/5257 Tested-by: jenkins

target: fix crash with jimtcl 0.78

2020-03-12T10:03:57Z

The jimtcl commit 41c5ff1809f5 ("jim.c: Fix Object leak in zlib support") https://repo.or.cz/jimtcl.git/commit/41c5ff1809f5 makes Jim_SetResultFormatted() freeing the parameters that have zero refcount. OpenOCD commit 559d08c19ed8 ("jim tests: use installed") adds the only code instance in OpenOCD that first passes a zero refcount object to Jim_SetResultFormatted() and then frees it. By switching jimtcl version to 0.78 or newer this causes a crash of OpenOCD. To trigger the crash in a telnet session, check that the current target is running and type: [target current] arp_waitstate halted 1 Remove the call to Jim_FreeNewObj() after the call to Jim_SetResultFormatted(). Change-Id: I5f5a8bca96a0e8466ff7b789fe578ea9785fa550 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5453 Tested-by: jenkins Reviewed-by: Tomas Vanek

semihosting: add semihosting handlers to AArch64

2020-03-12T09:48:56Z

note: this works only when the PE is in AArch64 state Change-Id: Id6a336ca7d201df72bd1aaaeccce4185473fc1bd Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/5474 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid Reviewed-by: Antonio Borneo

cortex_a: warn on broken debug_base setting

2020-03-12T09:48:25Z

A common problem with target configurations appears to be broken debug base address configuration. ARM DDI0406C.d specifies in App. D, 1.4.1, that bit 31 of the debug base address serves as identification of an external debugger, as opposed to an internal access to memory mapped debug registers by the CPU. External accesses are treated as privileged and require no debug authentification via the lock access register. Sometimes the base address of a debug component is wrong even in the targets' ROM table. In this case, the correct base address must be specified using the -dbgbase argument when creating the target. This patch adds a warning when bit 31 of the debug base address is not set, as a hint to the user. Change-Id: I9c41d85a138123c657ef655e3436a2aa39249dcc Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/5105 Tested-by: jenkins Reviewed-by: Tommy Vestermark Reviewed-by: Antonio Borneo

target/armv8_opcodes: use T32 instructions when the PE is in AArch32 state

2020-03-12T09:47:08Z

As stated in ARM v8-A Architecture Reference Manual (ARM DDI 0487E.a) in Chapter H4.3 DCC and ITR access modes: Writes to EDITR trigger the instruction to be executed if the PE is in Debug state: - If the PE is in AArch64 state, this is an A64 instruction. - If the PE is in AArch32 state, this is a T32 instruction But in armv8_opcodes specifically in t32_opcodes we were using some A32 instructions for HLT, LDRx and STRx opcodes. Using the correct LDRx and STRx opcodes, fixes 16 and 8 bits memory access when the PE is in AArch32 state. Change-Id: Ib1acbdd4966297e7b069569bcb8deea3c3993615 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/5346 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid Reviewed-by: Antonio Borneo

target/aarch64: fix soft breakpoint when PE is in AArch32 state

2020-03-12T09:46:43Z

Before this patch aarch64_set_breakpoint was using either A64, or A32 HLT opcode by relying on armv8_opcode helper. This behaviors ignores the fact that in AArch32 state the core could execute Thumb-2 instructions, and gdb could request to insert a soft bkpt in a Thumb-2 code chunk. In this change, we check the core_state and bkpt length to know the correct opcode to use. Note: based on https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html if bkpt length/kind == 3, we should replace a 32-bit Thumb-2 opcode, then we use twice the 16 bits Thumb-2 bkpt opcode and we fix-up the length to 4 bytes, in order to set correctly the bpkt. Change-Id: I8f3551124412c61d155eae87761767e9937f917d Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/5355 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid Reviewed-by: Antonio Borneo