OpenOCD/contrib, branch master

Flash driver for STM32G0xx and STM32G4xx

2020-03-16T15:25:10Z

Flash module of STM32G0/G4 family is quite similar to the one of STM32L4, so only minor changes are required, in particular adaption of flash loader to Cortex-M0. Register addresses passed to flash loader to simplify integration of L5. Added re-probe after option byte load. Added flash size override via cfg file. WRPxxR mask now based on max. number of pages instead of fixed 0xFF, as G4 devices fill up unused bits with '1'. Sizes in stm32l4_probe changed to multiples of 1kB. Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE. Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB. This handling isn't optimal as the bank size includes the size of the gap. WB not tested. Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593 Signed-off-by: Andreas Bolsch Reviewed-on: http://openocd.zylin.com/4807 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI Reviewed-by: Tomas Vanek

bluenrg-x: simplyfied the driver

2020-03-07T15:31:09Z

Adopted only fast algorithm for flash programming: - write_word and write_byte methods have been removed. - start and end write alignments have been defined. Moved flash controller registers offsets in a common file shared with the flash algorithm. - the flash base address is passed to the flash algorithm as a parameter. Removed unused functions Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491 Signed-off-by: luca vinci Reviewed-on: http://openocd.zylin.com/5393 Tested-by: jenkins Reviewed-by: Tomas Vanek Reviewed-by: Michele Sardo

bluenrg-x: added support for BlueNRG-LP device

2020-03-07T15:31:02Z

Extended bluenrg-x flash driver with BlueNRG-LP flash controller. Changes include: - register set for the flash controller - made software structure prone to support more easily future devices - updated target config file Change-Id: I2e2dc70db32cf98c62e3a43f2e44a4600a25ac5b Signed-off-by: luca vinci Reviewed-on: http://openocd.zylin.com/5343 Tested-by: jenkins Reviewed-by: Tomas Vanek

flash/stm32h7x: add support of STM32H7Ax/H7Bx devices

2020-03-02T15:13:00Z

this new device has the following features: - single core cortex-M7 - 2MB flash - dual bank - page size 8k - write protection grouped by 4 sectors - write block size 128 bits (16 bytes) the bit definition of FLASH_CR is different than STM32H74x, that's why we introduced a helper to compute the FLASH_CR value Change-Id: I4da10cde8dd215b1b0f2645f0efdba9d198038d1 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/5441 Tested-by: jenkins Reviewed-by: Tomas Vanek

coding style: add newline at end of text files

2020-02-24T10:30:53Z

Some text file is missing newline at EOF. Add it. Change-Id: Ieebc790096f40961283c644642e56fde975e957f Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5167 Tested-by: jenkins

flash/nor/stm32l4x: fix minor errors in flash write/async algo

2020-01-27T17:03:40Z

Fix comment of tested errors in asm src. List all relevant errors in FLASH_ERROR mask: FLASH_PROGERR was missing and any trial to re-program already programmed double word ended up in the error bit held uncleared and flash write permanetly repeating the error message until reset. Lock the bank also after unsuccesfull write_block run. Set async target algo block size to size of double word. Remove warning in case of write_block success. In case of error use LOG_ERROR instead of warning. Change-Id: Ibf6d5e306a4c2eaa43de67d636b4902c737f02f3 Signed-off-by: Tomas Vanek Reviewed-on: http://openocd.zylin.com/5360 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI

flash/nor/sh_qspi: Add SH QSPI driver

2020-01-22T05:50:20Z

Add driver for the SH QSPI controller. This SPI controller is often connected to the boot SPI NOR flash on R-Car Gen2 platforms. Add the following two lines to board TCL file to bind the driver on R-Car Gen2 SoC and make SRAM work area available: flash bank flash0 sh_qspi 0xe6b10000 0 0 0 ${_TARGETNAME}0 cs0 ${_TARGETNAME}0 configure -work-area-phys 0xe6300000 -work-area-virt 0xe6300000 -work-area-size 0x10000 -work-area-backup 0 To install mainline U-Boot on the board, use the following procedure: proc update_uboot {} { # SPL flash erase_sector 0 0x0 0x0 flash write_bank 0 /u-boot/spl/u-boot-spl.bin 0x0 # U-Boot flash erase_sector 0 0x5 0x6 flash write_bank 0 /u-boot/u-boot.img 0x140000 } Change-Id: Ief22f61e93bcabae37f6e371156dece6c4be3459 Signed-off-by: Marek Vasut --- V2: - Add Makefile and linker script for the SH QSPI IO algorithm - Include the algorithm code instead of hard-coding it Reviewed-on: http://openocd.zylin.com/5143 Tested-by: jenkins Reviewed-by: Oleksij Rempel

contrib/rpc_examples: Add (dis)connect methods

2020-01-02T21:21:12Z

Add these methods such that the OpenOcd class can also be used outside of a 'with' statement. Change-Id: I927c93fff2dc05cc74daa56360a7262e736a639f Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/5189 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tomas Vanek

target/stm32h7x: add support of dual core variant of STM32H7

2019-12-07T13:07:00Z

STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4 The second core creation is only done when * DUAL_CORE variable is set to true * non HLA interface is used A second check for the second core existence is done in cpu1 examine-end Once the second core is detected it gets examined. Furthermore, the script provides a configurable CTI usage in order to halt the cores simultaneously. Tested on Rev X and V devices. PS: the indentation was a mix of spaces and tabs, all changed to tabs. Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/5130 Tested-by: jenkins Reviewed-by: Tomas Vanek

STM8 Target relicensing to GPLv2 and later

2019-11-07T08:21:40Z

Change-Id: I21126945c0475399aaf12239b8972fde5fddd845 Signed-off-by: Ake Rehnman Reviewed-on: http://openocd.zylin.com/5331 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tomas Vanek Reviewed-by: Tarek BOCHKATI