OpenOCD, branch master

flash/startup.tcl: add STM32G0 and G4 aliases

2020-03-16T15:26:03Z

STM32G0 and G4 uses the same flash driver as the stm32l4x Change-Id: Ic1c4be70aaee809536912e0390f07893efb9a082 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/5482 Tested-by: jenkins Reviewed-by: Tomas Vanek

Flash driver for STM32G0xx and STM32G4xx

2020-03-16T15:25:10Z

Flash module of STM32G0/G4 family is quite similar to the one of STM32L4, so only minor changes are required, in particular adaption of flash loader to Cortex-M0. Register addresses passed to flash loader to simplify integration of L5. Added re-probe after option byte load. Added flash size override via cfg file. WRPxxR mask now based on max. number of pages instead of fixed 0xFF, as G4 devices fill up unused bits with '1'. Sizes in stm32l4_probe changed to multiples of 1kB. Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE. Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB. This handling isn't optimal as the bank size includes the size of the gap. WB not tested. Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593 Signed-off-by: Andreas Bolsch Reviewed-on: http://openocd.zylin.com/4807 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI Reviewed-by: Tomas Vanek

tcl/target: Fix naming of RZ/A1 SoC

2020-03-14T20:39:47Z

The RZ/A1 is not part of the R-Car family, but is rather an RZ family. Fix the naming. Change-Id: I5f882b2467e87e534e0f1c827554e664a7d55664 Signed-off-by: Marek Vasut Reviewed-on: http://openocd.zylin.com/5445 Tested-by: jenkins Reviewed-by: Oleksij Rempel

drivers: xds110: Fix errors in routine that toggles

2020-03-14T19:16:42Z

TCK during nSRST assert/deassert code. To support LPRF targets (CC13xx/CC26xx), TCK must be toggled for 50 ms while nSRST is asserted and right after it is released. This allows the core to halt in boot ROM before code is run that might interfere with debug access. The current routine has two issues. It shouldn't be run at all if the target is using SWD. And the delay needs to be a real-time 50 ms, so the number of TCK periods should be calculated off the set speed. Change-Id: If993031b84cf2a505ea67a6633602c4b01cd8e1e Signed-off-by: Edward Fewell Reviewed-on: http://openocd.zylin.com/5497 Tested-by: jenkins Reviewed-by: Tomas Vanek

target/cortex_a: add hypervisor mode

2020-03-12T10:11:19Z

Hypervisor mode is present only if the optional virtualization extensions are available. Moreover, virtualization extensions require that also security extensions are implemented. Add the required infrastructure for the shadowed registers in hypervisor mode. Make monitor shadowed registers visible in hypervisor mode too. Make hypervisor shadowed registers visible in hypervisor mode only. Check during cortex_a examine if virtualization extensions are present and then conditionally enable the visibility of both hypervisor and monitor modes shadowed registers. Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5261 Tested-by: jenkins

armv7a: access monitor registers only with security extensions

2020-03-12T10:10:33Z

Accordingly to ARM DDI 0406C at B1.5, the security extensions for armv7a are optional extensions and can be detected by reading ID_PFR1. The monitor mode is part of the security extensions and the shadow registers "sp_mon", "lr_mon" and "spsr_mon" are only present with the security extensions. Read the register ID_PFR1 during cortex_a examine, determine if security extension is present and then conditionally enable the visibility of the monitor mode shadow registers. Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5259 Tested-by: jenkins

target/armv4_5: remove unused macro

2020-03-12T10:09:15Z

The macro ARMV4_5_CORE_REG_MODENUM() is unused. Remove it! Change-Id: I183df57bd86c9428710ea3583e43fba88fd26e0a Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5260 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid

arm: Use different enum for core_type and core_mode

2020-03-12T10:05:42Z

The fields core_type and core_mode use the same enum arm_mode but encode different information, making the code less immediate to read. Use a different enum arm_core_type for the field core_type. The code behavior is not changed. Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5258 Tested-by: jenkins

arm: fix reg num for Monitor mode

2020-03-12T10:05:30Z

Commit 2efb1f14f611 ("Add GDB remote target description support for ARM4") inserts two additional registers "sp" and "lr" in the table arm_core_regs[], thus shifting by two the position of the last three registers already present "sp_mon" moved from index 37 to 39 "lr_mon" moved from index 38 to 40 "spsr_mon" moved from index 39 to 41 Part of the code is updated (e.g. enum defining ARM_SPSR_MON and array arm_mon_indices[]), but it's missing the update of mapping in armv4_5_core_reg_map[]. Fix armv4_5_core_reg_map[]. Change-Id: I0bdf766183392eb738206b876cd9559aacc29fa0 Signed-off-by: Antonio Borneo Fixes: 2efb1f14f611 ("Add GDB remote target description support for ARM4") Reviewed-on: http://openocd.zylin.com/5257 Tested-by: jenkins

ftdi: flush mpsse queue after a level change on reset pins

2020-03-12T10:05:09Z

The function ftdi_set_signal() does not propagate the pin change until next call to mpsse_flush(). Current code does not toggles immediately the reset pins if polling is turned off. Call mpsse_flush() at the end of ftdi_reset(). While there, remove the duplicated LOG message. Change-Id: I79eacfe4fc32b5cdf2dc1b78f3660d96988466bc Fixes: 8850eb8f2c51 ("swd: get rid of jtag queue to assert/deassert srst") Reported-by: Leonard Crestez Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/5431 Tested-by: jenkins Reviewed-by: Leonard Crestez Reviewed-by: Tomas Vanek