path: root/lib/Target/NVPTX/NVPTXVector.td

//===- NVPTXVector.td - NVPTX Vector Specific Instruction defs -*- tblgen-*-==//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//-----------------------------------
// Vector Specific
//-----------------------------------

//
// All vector instructions derive from NVPTXVecInst
//

class NVPTXVecInst<dag outs, dag ins, string asmstr, list<dag> pattern,
  NVPTXInst sInst=NOP>
  : NVPTXInst<outs, ins, asmstr, pattern> {
  NVPTXInst scalarInst=sInst;
}

let isAsCheapAsAMove=1, VecInstType=isVecExtract.Value in {
// Extract v2i16
def V2i16Extract : NVPTXVecInst<(outs Int16Regs:$dst),
  (ins V2I16Regs:$src, i8imm:$c),
                         "mov.u16 \t$dst, $src${c:vecelem};",
                         [(set Int16Regs:$dst, (vector_extract
                           (v2i16 V2I16Regs:$src), imm:$c))],
                         IMOV16rr>;

// Extract v4i16
def V4i16Extract : NVPTXVecInst<(outs Int16Regs:$dst),
  (ins V4I16Regs:$src, i8imm:$c),
                         "mov.u16 \t$dst, $src${c:vecelem};",
                         [(set Int16Regs:$dst, (vector_extract
                           (v4i16 V4I16Regs:$src), imm:$c))],
                         IMOV16rr>;

// Extract v2i8
def V2i8Extract : NVPTXVecInst<(outs Int8Regs:$dst),
  (ins V2I8Regs:$src, i8imm:$c),
                         "mov.u16 \t$dst, $src${c:vecelem};",
                         [(set Int8Regs:$dst, (vector_extract
                           (v2i8 V2I8Regs:$src), imm:$c))],
                         IMOV8rr>;

// Extract v4i8
def V4i8Extract : NVPTXVecInst<(outs Int8Regs:$dst),
  (ins V4I8Regs:$src, i8imm:$c),
                         "mov.u16 \t$dst, $src${c:vecelem};",
                         [(set Int8Regs:$dst, (vector_extract
                           (v4i8 V4I8Regs:$src), imm:$c))],
                         IMOV8rr>;

// Extract v2i32
def V2i32Extract : NVPTXVecInst<(outs Int32Regs:$dst),
  (ins V2I32Regs:$src, i8imm:$c),
                         "mov.u32 \t$dst, $src${c:vecelem};",
                         [(set Int32Regs:$dst, (vector_extract
                           (v2i32 V2I32Regs:$src), imm:$c))],
                         IMOV32rr>;

// Extract v2f32
def V2f32Extract : NVPTXVecInst<(outs Float32Regs:$dst),
  (ins V2F32Regs:$src, i8imm:$c),
                         "mov.f32 \t$dst, $src${c:vecelem};",
                         [(set Float32Regs:$dst, (vector_extract
                           (v2f32 V2F32Regs:$src), imm:$c))],
                         FMOV32rr>;

// Extract v2i64
def V2i64Extract : NVPTXVecInst<(outs Int64Regs:$dst),
  (ins V2I64Regs:$src, i8imm:$c),
                         "mov.u64 \t$dst, $src${c:vecelem};",
                         [(set Int64Regs:$dst, (vector_extract
                           (v2i64 V2I64Regs:$src), imm:$c))],
                         IMOV64rr>;

// Extract v2f64
def V2f64Extract : NVPTXVecInst<(outs Float64Regs:$dst),
  (ins V2F64Regs:$src, i8imm:$c),
                         "mov.f64 \t$dst, $src${c:vecelem};",
                         [(set Float64Regs:$dst, (vector_extract
                           (v2f64 V2F64Regs:$src), imm:$c))],
                         FMOV64rr>;

// Extract v4i32
def V4i32Extract : NVPTXVecInst<(outs Int32Regs:$dst),
  (ins V4I32Regs:$src, i8imm:$c),
                         "mov.u32 \t$dst, $src${c:vecelem};&q