path: root/lib/Target/Alpha/AlphaInstrInfo.td

//===- AlphaInstrInfo.td - The Alpha Instruction Set -------*- tablegen -*-===//
// 
//                     The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
// 
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//

include "AlphaInstrFormats.td"

//********************
//Custom DAG Nodes
//********************

def SDTFPUnaryOpUnC  : SDTypeProfile<1, 1, [
  SDTCisFP<1>, SDTCisFP<0>
]>;
def Alpha_cvtqt   : SDNode<"AlphaISD::CVTQT_",    SDTFPUnaryOpUnC, []>;
def Alpha_cvtqs   : SDNode<"AlphaISD::CVTQS_",    SDTFPUnaryOpUnC, []>;
def Alpha_cvttq   : SDNode<"AlphaISD::CVTTQ_"  ,  SDTFPUnaryOp, []>;
def Alpha_gprello : SDNode<"AlphaISD::GPRelLo",   SDTIntBinOp, []>;
def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi",   SDTIntBinOp, []>;
def Alpha_rellit  : SDNode<"AlphaISD::RelLit",    SDTIntBinOp, []>;

def retflag       : SDNode<"AlphaISD::RET_FLAG", SDTRet,
	                   [SDNPHasChain, SDNPOptInFlag]>;

// These are target-independent nodes, but have target-specific formats.
def SDT_AlphaCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64> ]>;
def SDT_AlphaCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i64>,
                                           SDTCisVT<1, i64> ]>;

def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeqStart,
    		           [SDNPHasChain, SDNPOutFlag]>;
def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_AlphaCallSeqEnd,
                           [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;

//********************
//Paterns for matching
//********************
def invX : SDNodeXForm<imm, [{ //invert
  return getI64Imm(~N->getValue());
}]>;
def negX : SDNodeXForm<imm, [{ //negate
  return getI64Imm(~N->getValue() + 1);
}]>;
def SExt32 : SDNodeXForm<imm, [{ //signed extend int to long
  return getI64Imm(((int64_t)N->getValue() << 32) >> 32);
}]>;
def SExt16 : SDNodeXForm<imm, [{ //signed extend int to long
  return getI64Imm(((int64_t)N->getValue() << 48) >> 48);
}]>;
def LL16 : SDNodeXForm<imm, [{ //lda part of constant
  return getI64Imm(get_lda16(N->getValue()));
}]>;
def LH16 : SDNodeXForm<imm, [{ //ldah part of constant (or more if too big)
  return getI64Imm(get_ldah16(N->getValue()));
}]>;
def iZAPX : SDNodeXForm<and, [{ // get imm to ZAPi
  ConstantSDNode *RHS = cast<ConstantSDNode>(N->getOperand(1));
  return getI64Imm(get_zapImm(SDOperand(), RHS->getValue()));
}]>;
def nearP2X : SDNodeXForm<imm, [{
  return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getValue())));
}]>;
def nearP2RemX : SDNodeXForm<imm, [{
  uint64_t x = abs(N->getValue() - getNearPower2((uint64_t)N->getValue()));
  return getI64Imm(Log2_64(x));
}]>;

def immUExt8  : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field
  return (uint64_t)N->getValue() == (uint8_t)N->getValue();
}]>;
def immUExt8inv  : PatLeaf<(imm), [{ //inverted imm fits in 8 bit zero extended field
  return (uint64_t)~N->getValue() == (uint8_t)~N->getValue();
}], invX>;
def immUExt8neg  : PatLeaf<(imm), [{ //negated imm fits in 8 bit zero extended field
  return ((uint64_t)~N->getValue() + 1) == (uint8_t)((uint64_t)~N->getValue() + 1);
}], negX>;
def immSExt16  : PatLeaf<(imm), [{ //imm fits in 16 bit sign extended field
  return ((int64_t)N->getValue() << 48) >> 48 == (int64_t)N->getValue();
}]>;
def immSExt16int  : PatLeaf<(imm), [{ //(int)imm fits in a 16 bit sign extended field
  return ((int64_t)N->getValue() << 48) >> 48 == ((int64_t)N->getValue() << 32) >> 32;
}], SExt16>;

def zappat : PatFrag<(ops node:$LHS), (and node:$LHS, imm:$L), [{
  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
    uint64_t build = get_zapImm(N->getOperand(0), (uint64_t)RHS->getValue());
    return build != 0;
  }
  return false;
}]>;

def immFPZ  : PatLeaf<(fpimm), [{ //the only fpconstant nodes are +/- 0.0
  (void)N; // silence warning.
  return true;
}]>;

def immRem1  : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),1, 0);}]>;
def immRem2  : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),2, 0);}]>;
def immRem3  : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),3, 0);}]>;
def immRem4  : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),4, 0);}]>;
def immRem5  : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),5, 0);}]>;
def immRem1n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),1, 1);}]>;
def immRem2n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),2, 1);}]>;
def immRem3n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),3, 1);}]>;
def immRem4n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),4, 1);}]>;
def immRem5n : PatLeaf<(imm), [{return chkRemNearPower2(N->getValue(),5, 1);}]>;

def immRemP2n : PatLeaf<(imm), [{
  return isPowerOf2_64(getNearPower2((uint64_t)N->getValue()) - N->getValue());
}]>;
def immRemP2 : PatLeaf<(imm), [{
  return isPowerOf2_64(N->getValue() - getNearPower2((uint64_t)N->getValue()));
}]>;
def immUExt8ME : PatLeaf<(imm), [{ //use this imm for mulqi
  int64_t d =  abs((int64_t)N->getValue() - (int64_t)getNearPower2((uint64_t)N->getValue()));
  if (isPowerOf2_64(d)) return false;
  switch (d) {
    case 1: case 3: case 5: return false; 
    default: return (uint64_t)N->getValue() == (uint8_t)N->getValue();
  };
}]>;

def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>;
def add4  : PatFrag<(ops node:$op1, node:$op2),
                    (add (shl node:$op1, 2), node:$op2)>;
def sub4  : PatFrag<(ops node:$op1, node:$op2),
                    (sub (shl node:$op1, 2), node:$op2)>;
def add8  : PatFrag<(ops node:$op1, node:$op2),
                    (add (shl node:$op1, 3), node:$op2)>;
def sub8  : PatFrag<(ops node:$op1, node:$op2),
                    (sub (shl node:$op1, 3), node:$op2)>;
class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
class CmpOpFrag<dag res> : PatFrag<(ops node:$R), res>;

//Pseudo ops for selection

def IDEF_I : PseudoInstAlpha<(outs GPRC:$RA), (ins), ";#idef $RA",
             [(set GPRC:$RA, (undef))], s_pseudo>;
def IDEF_F32 : PseudoInstAlpha<(outs F4RC:$RA), (ins), ";#idef $RA",
             [(set F4RC:$RA, (undef))], s_pseudo>;
def IDEF_F64 : PseudoInstAlpha<(outs F8RC:$RA), (ins), ";#idef $RA",
             [(set F8RC:$RA, (undef))], s_pseudo>;

def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;

let isLoad = 1, hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt),
                "; ADJUP $amt", 
                [(callseq_start imm:$amt)], s_pseudo>;
def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt1, s64imm:$amt2),
                "; ADJDOWN $amt1",
                [(callseq_end imm:$amt1, imm:$amt2)], s_pseudo>;
}

def ALTENT : PseudoInstAlpha<(outs), (ins s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>;
def PCLABEL : PseudoInstAlpha<(outs), (ins s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>;
def MEMLABEL : PseudoInstAlpha<(outs), (ins s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
         "LSMARKER$$$i$$$j$$$k$$$m:", [], s_pseudo>;


//***********************
//Real instructions
//***********************

//Operation Form:

//conditional moves, int

multiclass cmov_inst<bits<7> fun, string asmstr, PatFrag OpNode> {
def r : OForm4<0x11, fun, !strconcat(asmstr, " $RCOND,$RTRUE,$RDEST"),
             [(set GPRC:$RDEST, (select (OpNode GPRC:$RCOND), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
def i : OForm4L<0x11, fun, !strconcat(asmstr, " $RCOND,$RTRUE,$RDEST"),
             [(set GPRC:$RDEST, (select (OpNode GPRC:$RCOND), immUExt8:$RTRUE, GPRC:$RFALSE))], s_cmov>;
}

defm CMOVEQ  : cmov_inst<0x24, "cmoveq",  CmpOpFrag<(seteq node:$R, 0)>>;
defm CMOVNE  : cmov_inst<0x26, "cmovne",  CmpOpFrag<(setne node:$R, 0)>>;
defm CMOVLT  : cmov_inst<0x44, "cmovlt",  CmpOpFrag<(setlt node:$R, 0)>>;
defm CMOVLE  : cmov_inst<0x64, "cmovle",  CmpOpFrag<(setle node:$R, 0)>>;
defm CMOVGT  : cmov_inst<0x66, "cmovgt",  CmpOpFrag<(setgt node:$R, 0)>>;
defm CMOVGE  : cmov_inst<0x46, "cmovge",  CmpOpFrag<(setge node:$R, 0)>>;
defm CMOVLBC : cmov_inst<0x16, "cmovlbc", CmpOpFrag<(xor   node:$R, 1)>>;
defm CMOVLBS : cmov_inst<0x14, "cmovlbs", CmpOpFrag<(and   node:$R, 1)>>;

//General pattern for cmov
def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
      (CMOVNEr GPRC:$src2, GPRC:$src1, GPRC:$which)>;
def : Pat<(select GPRC:$which, GPRC:$src1, immUExt8:$src2),
      (CMOVEQi GPRC:$src1, immUExt8:$src2, GPRC:$which)>;

//Invert sense when we can for constants:
def : Pat<(select (setne GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
          (CMOVEQi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
def : Pat<(select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
          (CMOVLEi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
def : Pat<(select (setge GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
          (CMOVLTi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
def : Pat<(select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
          (CMOVGEi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
def : Pat<(select (setle GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
          (CMOVGTi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;

multiclass all_inst<bits<6> opc, bits<7> funl, bits<7> funq, 
                    string asmstr, PatFrag OpNode, InstrItinClass itin> {
  def Lr : OForm< opc, funl, !strconcat(asmstr, "l $RA,$RB,$RC"),
               [(set GPRC:$RC, (intop (OpNode GPRC:$RA, GPRC:$RB)))], itin>;
  def Li : OFormL<opc, funl, !strconcat(asmstr, "l $RA,$L,$RC"),
               [(set GPRC:$RC, (intop (OpNode GPRC:$RA, immUExt8:$L)))], itin>;
  def Qr : OForm< opc, funq, !strconcat(asmstr, "q $RA,$RB,$RC"),
               [(set GPRC:$RC, (OpNode GPRC:$RA, GPRC:$RB))], itin>;
  def Qi : OFormL<opc, funq, !strconcat(asmstr, "q $RA,$L,$RC"),
               [(set GPRC:$RC, (OpNode GPRC:$RA, immUExt8:$L))], itin>;
}

defm MUL   : all_inst<0x13, 0x00, 0x20, "mul",   BinOpFrag<(mul node:$LHS, node:$RHS)>, s_imul>;
defm ADD   : all_inst<0x10, 0x00, 0x20, "add",   BinOpFrag<(add node:$LHS, node:$RHS)>, s_iadd>;
defm S4ADD : all_inst<0x10, 0x02, 0x22, "s4add", add4, s_iadd>;
defm S8ADD : all_inst<0x10, 0x12, 0x32, "s8add", add8, s_iadd>;
defm S4SUB : all_inst<0x10, 0x0B, 0x2B, "s4sub", sub4, s_iadd>;
defm S8SUB : all_inst<0x10, 0x1B, 0x3B, "s8sub", sub8, s_iadd>;
defm SUB   : all_inst<0x10, 0x09, 0x29, "sub",   BinOpFrag<(sub node:$LHS, node:$RHS)>, s_iadd>;
//Const cases since legalize does sub x, int -> add x, inv(int) + 1
def : Pat<(intop (add GPRC:$RA, immUExt8neg:$L)), (SUBLi GPRC:$RA, immUExt8neg:$L)>;
def : Pat<(add GPRC:$RA, immUExt8neg:$L), (SUBQi GPRC:$RA, immUExt8neg:$L)>;
def : Pat<(intop (add4 GPRC:$RA, immUExt8neg:$L)), (S4SUBLi GPRC:$RA, immUExt8neg:$L)>;
def : Pat<(add4 GPRC:$RA, immUExt8neg:$L), (S4SUBQi GPRC:$RA, immUExt8neg:$L)>;
def : Pat<(intop (add8 GPRC:$RA, immUExt8neg:$L)), (S8SUBLi GPRC:$RA, immUExt8neg:$L)>;
def : Pat<(add8 GPRC:$RA, immUExt8neg:$L), (S8SUBQi GPRC:$RA, immUExt8neg:$L)>;

multiclass log_inst<bits<6> opc, bits<7> fun, string asmstr, SDNode OpNode, InstrItinClass itin> {
def r : OForm<opc, fun, !strconcat(asmstr, " $RA,$RB,$RC"),
              [(set GPRC:$RC, (OpNode GPRC:$RA, GPRC:$RB))], itin>;
def i : OFormL<opc, fun, !strconcat(asmstr, " $RA,$L,$RC"),
              [(set GPRC:$RC, (OpNode GPRC:$RA, immUExt8:$L))], itin>;
}
multiclass inv_inst<bits<6> opc, bits<7> fun, string asmstr, SDNode OpNode, InstrItinClass itin> {
def r : OForm<opc, fun, !strconcat(asmstr, " $RA,$RB,$RC"),
              [(set GPRC:$RC, (OpNode GPRC:$RA, (not GPRC:$RB)))], itin>;
def i : OFormL<opc, fun, !strconcat(asmstr, " $RA,$L,$RC"),
              [(set GPRC:$RC, (OpNode GPRC:$RA, immUExt8inv:$L))], itin>;
}

defm AND   : log_inst<0x11, 0x00, "and",   and,   s_ilog>;
defm BIC   : inv_inst<0x11, 0x08, "bic",   and,   s_ilog>;
defm BIS   : log_inst<0x11, 0x20, "bis",   or,    s_ilog>;
defm ORNOT : inv_inst<0x11, 0x28, "ornot", or,    s_ilog>;
defm XOR   : log_inst<0x11, 0x40, "xor",   xor,   s_ilog>;
defm EQV   : inv_inst<0x11, 0x48, "eqv",   xor,   s_ilog>;

defm SL    : log_inst<0x12, 0x39, "sll",   shl,   s_ishf>;
defm SRA   : log_inst<0x12, 0x3c, "sra",   sra,   s_ishf>;
defm SRL   : log_inst<0x12, 0x34, "srl",   srl,   s_ishf>;
defm UMULH : log_inst<0x13, 0x30, "umulh", mulhu, s_imul>;

def CTLZ     : OForm2<0x1C, 0x32, "CTLZ $RB,$RC", 
                      [(set GPRC:$RC, (ctlz GPRC:$RB))], s_imisc>;
def CTPOP    : OForm2<0x1C, 0x30, "CTPOP $RB,$RC", 
                      [(set GPRC:$RC, (ctpop GPRC:$RB))], s_imisc>;
def CTTZ     : OForm2<0x1C, 0x33, "CTTZ $RB,$RC", 
                      [(set GPRC:$RC, (cttz GPRC:$RB))], s_imisc>;
def EXTBL    : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC", 
                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 255))], s_ishf>;
def EXTWL    : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC", 
                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 65535))], s_ishf>;
def EXTLL    : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC", 
                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 4294967295))], s_ishf>;
def SEXTB    : OForm2<0x1C, 0x00, "sextb $RB,$RC", 
                      [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))], s_ishf>;
def SEXTW    : OForm2<0x1C, 0x01, "sextw $RB,$RC", 
                      [(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))], s_ishf>;

//def EXTBLi   : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC", []>; //Extract byte low
//def EXTLH    : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC", []>; //Extract longword high
//def EXTLHi   : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC", []>; //Extract longword high
//def EXTLLi   : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC", []>; //Extract longword low
//def EXTQH    : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC", []>; //Extract quadword high
//def EXTQHi   : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC", []>; //Extract quadword high
//def EXTQ     : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC", []>; //Extract quadword low
//def EXTQi    : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC", []>; //Extract quadword low
//def EXTWH    : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC", []>; //Extract word high
//def EXTWHi   : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC", []>; //Extract word high
//def EXTWLi   : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC", []>; //Extract word low

//def INSBL    : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC", []>; //Insert byte low
//def INSBLi   : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC", []>; //Insert byte low
//def INSLH    : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC", []>; //Insert longword high
//def INSLHi   : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC", []>; //Insert longword high
//def INSLL    : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC", []>; //Insert longword low
//def INSLLi   : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC", []>; //Insert longword low
//def INSQH    : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC", []>; //Insert quadword high
//def INSQHi   : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC", []>; //Insert quadword high
//def INSQL    : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC", []>; //Insert quadword low
//def INSQLi   : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC", []>; //Insert quadword low
//def INSWH    : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC", []>; //Insert word high
//def INSWHi   : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC", []>; //Insert word high
//def INSWL    : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC", []>; //Ins