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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
"http://www.w3.org/TR/html4/strict.dtd">
<html>
<head>
<title>TableGen Fundamentals</title>
<link rel="stylesheet" href="llvm.css" type="text/css">
</head>
<body>
<h1>TableGen Fundamentals</h1>
<div>
<ul>
<li><a href="#introduction">Introduction</a>
<ol>
<li><a href="#concepts">Basic concepts</a></li>
<li><a href="#example">An example record</a></li>
<li><a href="#running">Running TableGen</a></li>
</ol></li>
<li><a href="#syntax">TableGen syntax</a>
<ol>
<li><a href="#primitives">TableGen primitives</a>
<ol>
<li><a href="#comments">TableGen comments</a></li>
<li><a href="#types">The TableGen type system</a></li>
<li><a href="#values">TableGen values and expressions</a></li>
</ol></li>
<li><a href="#classesdefs">Classes and definitions</a>
<ol>
<li><a href="#valuedef">Value definitions</a></li>
<li><a href="#recordlet">'let' expressions</a></li>
<li><a href="#templateargs">Class template arguments</a></li>
<li><a href="#multiclass">Multiclass definitions and instances</a></li>
</ol></li>
<li><a href="#filescope">File scope entities</a>
<ol>
<li><a href="#include">File inclusion</a></li>
<li><a href="#globallet">'let' expressions</a></li>
</ol></li>
</ol></li>
<li><a href="#backends">TableGen backends</a>
<ol>
<li><a href="#">todo</a></li>
</ol></li>
</ul>
</div>
<div class="doc_author">
<p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
</div>
<!-- *********************************************************************** -->
<h2><a name="introduction">Introduction</a></h2>
<!-- *********************************************************************** -->
<div>
<p>TableGen's purpose is to help a human develop and maintain records of
domain-specific information. Because there may be a large number of these
records, it is specifically designed to allow writing flexible descriptions and
for common features of these records to be factored out. This reduces the
amount of duplication in the description, reduces the chance of error, and
makes it easier to structure domain specific information.</p>
<p>The core part of TableGen <a href="#syntax">parses a file</a>, instantiates
the declarations, and hands the result off to a domain-specific "<a
href="#backends">TableGen backend</a>" for processing. The current major user
of TableGen is the <a href="CodeGenerator.html">LLVM code generator</a>.</p>
<p>Note that if you work on TableGen much, and use emacs or vim, that you can
find an emacs "TableGen mode" and a vim language file in the
<tt>llvm/utils/emacs</tt> and <tt>llvm/utils/vim</tt> directories of your LLVM
distribution, respectively.</p>
<!-- ======================================================================= -->
<h3><a name="concepts">Basic concepts</a></h3>
<div>
<p>TableGen files consist of two key parts: 'classes' and 'definitions', both
of which are considered 'records'.</p>
<p><b>TableGen records</b> have a unique name, a list of values, and a list of
superclasses. The list of values is the main data that TableGen builds for each
record; it is this that holds the domain specific information for the
application. The interpretation of this data is left to a specific <a
href="#backends">TableGen backend</a>, but the structure and format rules are
taken care of and are fixed by TableGen.</p>
<p><b>TableGen definitions</b> are the concrete form of 'records'. These
generally do not have any undefined values, and are marked with the
'<tt>def</tt>' keyword.</p>
<p><b>TableGen classes</b> are abstract records that are used to build and
describe other records. These 'classes' allow the end-user to build
abstractions for either the domain they are targeting (such as "Register",
"RegisterClass", and "Instruction" in the LLVM code generator) or for the
implementor to help factor out common properties of records (such as "FPInst",
which is used to represent floating point instructions in the X86 backend).
TableGen keeps track of all of the classes that are used to build up a
definition, so the backend can find all definitions of a particular class, such
as "Instruction".</p>
<p><b>TableGen multiclasses</b> are groups of abstract records that are
instantiated all at once. Each instantiation can result in multiple
TableGen definitions. If a multiclass inherits from another multiclass,
the definitions in the sub-multiclass become part of the current
multiclass, as if they were declared in the current multiclass.</p>
</div>
<!-- ======================================================================= -->
<h3><a name="example">An example record</a></h3>
<div>
<p>With no other arguments, TableGen parses the specified file and prints out
all of the classes, then all of the definitions. This is a good way to see what
the various definitions expand to fully. Running this on the <tt>X86.td</tt>
file prints this (at the time of this writing):</p>
<div class="doc_code">
<pre>
...
<b>def</b> ADD32rr { <i>// Instruction X86Inst I</i>
<b>string</b> Namespace = "X86";
<b>dag</b> OutOperandList = (outs GR32:$dst);
<b>dag</b> InOperandList = (ins GR32:$src1, GR32:$src2);
<b>string</b> AsmString = "add{l}\t{$src2, $dst|$dst, $src2}";
<b>list</b><dag> Pattern = [(set GR32:$dst, (add GR32:$src1, GR32:$src2))];
<b>list</b><Register> Uses = [];
<b>list</b><Register> Defs = [EFLAGS];
<b>list</b><Predicate> Predicates = [];
<b>int</b> CodeSize = 3;
<b>int</b> AddedComplexity = 0;
<b>bit</b> isReturn = 0;
<b>bit</b> isBranch = 0;
<b>bit</b> isIndirectBranch = 0;
<b>bit</b> isBarrier = 0;
<b>bit</b> isCall = 0;
<b>bit</b> canFoldAsLoad = 0;
<b>bit</b> mayLoad = 0;
<b>bit</b> mayStore = 0;
<b>bit</b> isImplicitDef = 0;
<b>bit</b> isConvertibleToThreeAddress = 1;
<b>bit</b> isCommutable = 1;
<b>bit</b> isTerminator = 0;
<b>bit</b> isReMaterializable = 0;
<b>bit</b> isPredicable = 0;
<b>bit</b> hasDelaySlot = 0;
<b>bit</b> usesCustomInserter = 0;
<b>bit</b> hasCtrlDep = 0;
<b>bit</b> isNotDuplicable = 0;
<b>bit</b> hasSideEffects = 0;
<b>bit</b> neverHasSideEffects = 0;
InstrItinClass Itinerary = NoItinerary;
<b>string</b> Constraints = "";
<b>string</b> DisableEncoding = "";
<b>bits</b><8> Opcode = { 0, 0, 0, 0, 0, 0, 0, 1 };
Format Form = MRMDestReg;
<b>bits</b><6> FormBits = { 0, 0, 0, 0, 1, 1 };
ImmType ImmT = NoImm;
<b>bits</b><3> ImmTypeBits = { 0, 0, 0 };
<b>bit</b> hasOpSizePrefix = 0;
<b>bit</b> hasAdSizePrefix = 0;
<b>bits</b><4> Prefix = { 0, 0, 0, 0 };
<b>bit</b> hasREX_WPrefix = 0;
FPFormat FPForm = ?;
<b>bits</b><3> FPFormBits = { 0, 0, 0 };
}
...
</pre>
</div>
<p>This definition corresponds to a 32-bit register-register add instruction in
the X86. The string after the '<tt>def</tt>' string indicates the name of the
record—"<tt>ADD32rr</tt>" in this case—and the comment at the end of
the line indicates the superclasses of the definition. The body of the record
contains all of the data that TableGen assembled for the record, indicating that
the instruction is part of the "X86" namespace, the pattern indicating how the
the instruction should be emitted into the assembly file, that it is a
two-address instruction, has a particular encoding, etc. The contents and
semantics of the information in the record is specific to the needs of the X86
backend, and is only shown as an example.</p>
<p>As you can see, a lot of information is needed for every instruction
supported by the code generator, and specifying it all manually would be
unmaintainable, prone to bugs, and tiring to do in the first place. Because we
are using TableGen, all of the information was derived from the following
definition:</p>
<div class="doc_code">
<pre>
let Defs = [EFLAGS],
is
|
