From 44a65fa552ed61cf9dba8f68f59b05e5137e6b01 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Tue, 16 May 2006 07:05:30 +0000
Subject: Allow patterns to refer to physical registers that belong to multiple
 register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28323 91177308-0d34-0410-b5e6-96231b3b80d8
---
 utils/TableGen/CodeGenTarget.cpp | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'utils/TableGen/CodeGenTarget.cpp')

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index de36eb0902..6916225b61 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -163,6 +163,23 @@ void CodeGenTarget::ReadRegisterClasses() const {
   RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
 }
 
+std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const {
+  std::vector<unsigned char> Result;
+  const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
+  for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
+    const CodeGenRegisterClass &RC = RegisterClasses[i];
+    for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
+      if (R == RC.Elements[ei]) {
+        const std::vector<MVT::ValueType> &InVTs = RC.getValueTypes();
+        for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
+          Result.push_back(InVTs[i]);
+      }
+    }
+  }
+  return Result;
+}
+
+
 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
   // Rename anonymous register classes.
   if (R->getName().size() > 9 && R->getName()[9] == '.') {
-- 
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