From 2661b411ccc81b1fe19194d3f43b2630cbef3f28 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Sat, 7 Jul 2012 04:00:00 +0000 Subject: I'm introducing a new machine model to simultaneously allow simple subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/CodeGenSchedule.cpp | 151 +++++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 utils/TableGen/CodeGenSchedule.cpp (limited to 'utils/TableGen/CodeGenSchedule.cpp') diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp new file mode 100644 index 0000000000..f57fd182ea --- /dev/null +++ b/utils/TableGen/CodeGenSchedule.cpp @@ -0,0 +1,151 @@ +//===- CodeGenSchedule.cpp - Scheduling MachineModels ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines structures to encapsulate the machine model as decribed in +// the target description. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "subtarget-emitter" + +#include "CodeGenSchedule.h" +#include "CodeGenTarget.h" +#include "llvm/Support/Debug.h" + +using namespace llvm; + +// CodeGenModels ctor interprets machine model records and populates maps. +CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK, + const CodeGenTarget &TGT): + Records(RK), Target(TGT), NumItineraryClasses(0), HasProcItineraries(false) { + + // Populate SchedClassIdxMap and set NumItineraryClasses. + CollectSchedClasses(); + + // Populate ProcModelMap. + CollectProcModels(); +} + +// Visit all the instruction definitions for this target to gather and enumerate +// the itinerary classes. These are the explicitly specified SchedClasses. More +// SchedClasses may be inferred. +void CodeGenSchedModels::CollectSchedClasses() { + + // NoItinerary is always the first class at Index=0 + SchedClasses.resize(1); + SchedClasses.back().Name = "NoItinerary"; + SchedClassIdxMap[SchedClasses.back().Name] = 0; + + // Gather and sort all itinerary classes used by instruction descriptions. + std::vector ItinClassList; + for (CodeGenTarget::inst_iterator I = Target.inst_begin(), + E = Target.inst_end(); I != E; ++I) { + Record *SchedDef = (*I)->TheDef->getValueAsDef("Itinerary"); + // Map a new SchedClass with no index. + if (!SchedClassIdxMap.count(SchedDef->getName())) { + SchedClassIdxMap[SchedDef->getName()] = 0; + ItinClassList.push_back(SchedDef); + } + } + // Assign each itinerary class unique number, skipping NoItinerary==0 + NumItineraryClasses = ItinClassList.size(); + std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); + for (unsigned i = 0, N = NumItineraryClasses; i < N; i++) { + Record *ItinDef = ItinClassList[i]; + SchedClassIdxMap[ItinDef->getName()] = SchedClasses.size(); + SchedClasses.push_back(CodeGenSchedClass(ItinDef)); + } + + // TODO: Infer classes from non-itinerary scheduler resources. +} + +// Gather all processor models. +void CodeGenSchedModels::CollectProcModels() { + std::vector ProcRecords = + Records.getAllDerivedDefinitions("Processor"); + std::sort(ProcRecords.begin(), ProcRecords.end(), LessRecordFieldName()); + + // Reserve space because we can. Reallocation would be ok. + ProcModels.reserve(ProcRecords.size()); + + // For each processor, find a unique machine model. + for (unsigned i = 0, N = ProcRecords.size(); i < N; ++i) + addProcModel(ProcRecords[i]); +} + +// Get a unique processor model based on the defined MachineModel and +// ProcessorItineraries. +void CodeGenSchedModels::addProcModel(Record *ProcDef) { + unsigned Idx = getProcModelIdx(ProcDef); + if (Idx < ProcModels.size()) + return; + + Record *ModelDef = ProcDef->getValueAsDef("SchedModel"); + Record *ItinsDef = ProcDef->getValueAsDef("ProcItin"); + + std::string ModelName = ModelDef->getName(); + const std::string &ItinName = ItinsDef->getName(); + + bool NoModel = ModelDef->getValueAsBit("NoModel"); + bool hasTopLevelItin = !ItinsDef->getValueAsListOfDefs("IID").empty(); + if (NoModel) { + // If an itinerary is defined without a machine model, infer a new model. + if (NoModel && hasTopLevelItin) { + ModelName = ItinName + "Model"; + ModelDef = NULL; + } + } + else { + // If a machine model is defined, the itinerary must be defined within it + // rather than in the Processor definition itself. + assert(!hasTopLevelItin && "Itinerary must be defined in SchedModel"); + ItinsDef = ModelDef->getValueAsDef("Itineraries"); + } + + ProcModelMap[getProcModelKey(ProcDef)]= ProcModels.size(); + + ProcModels.push_back(CodeGenProcModel(ModelName, ModelDef, ItinsDef)); + + std::vector ItinRecords = ItinsDef->getValueAsListOfDefs("IID"); + CollectProcItin(ProcModels.back(), ItinRecords); +} + +// Gather the processor itineraries. +void CodeGenSchedModels::CollectProcItin(CodeGenProcModel &ProcModel, + std::vector ItinRecords) { + // Skip empty itinerary. + if (ItinRecords.empty()) + return; + + HasProcItineraries = true; + + ProcModel.ItinDefList.resize(NumItineraryClasses+1); + + // Insert each itinerary data record in the correct position within + // the processor model's ItinDefList. + for (unsigned i = 0, N = ItinRecords.size(); i < N; i++) { + Record *ItinData = ItinRecords[i]; + Record *ItinDef = ItinData->getValueAsDef("TheClass"); + if (!SchedClassIdxMap.count(ItinDef->getName())) { + DEBUG(dbgs() << ProcModel.ItinsDef->getName() + << " has unused itinerary class " << ItinDef->getName() << '\n'); + continue; + } + ProcModel.ItinDefList[getItinClassIdx(ItinDef)] = ItinData; + } +#ifndef NDEBUG + // Check for missing itinerary entries. + assert(!ProcModel.ItinDefList[0] && "NoItinerary class can't have rec"); + for (unsigned i = 1, N = ProcModel.ItinDefList.size(); i < N; ++i) { + if (!ProcModel.ItinDefList[i]) + DEBUG(dbgs() << ProcModel.ItinsDef->getName() + << " missing itinerary for class " << SchedClasses[i].Name << '\n'); + } +#endif +} -- cgit v1.2.3-18-g5258