From 240b7f3324da70937d4fe6d0bd7278ae82849114 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Wed, 27 Mar 2013 06:52:27 +0000 Subject: Allocate r0 on PPC The R0 register can now be allocated because instructions that cannot use R0 as a GPR have been appropriately marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178123 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/allocate-r0.ll | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 test/CodeGen/PowerPC/allocate-r0.ll (limited to 'test/CodeGen/PowerPC') diff --git a/test/CodeGen/PowerPC/allocate-r0.ll b/test/CodeGen/PowerPC/allocate-r0.ll new file mode 100644 index 0000000000..1cf4cec076 --- /dev/null +++ b/test/CodeGen/PowerPC/allocate-r0.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(i64 %a) nounwind { +entry: + call void asm sideeffect "", "~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12}"() nounwind + br label %return + +; CHECK: @foo +; Because r0 is allocatable, we can use it to hold r3 without spilling. +; CHECK: mr 0, 3 +; CHECK: mr 3, 0 + +return: ; preds = %entry + ret i64 %a +} + -- cgit v1.2.3-18-g5258