From 4d53e7798c94143a22a9871261b8443592b929d5 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Tue, 12 Mar 2013 15:18:14 +0000 Subject: Don't reserve R2 on Darwin/PPC Now that only the register-scavenger version of the CR spilling code remains, we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in any case where the System V ABI uses it (R0 is special architecturally, and so is reserved under all common ABIs). A few test cases needed to be updated to reflect the register-allocation changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'test/CodeGen/PowerPC/2010-02-12-saveCR.ll') diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 974a99a52c..433fe5cc2a 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -6,17 +6,17 @@ target triple = "powerpc-apple-darwin9.6" define void @foo() nounwind { entry: -;CHECK: mfcr r2 -;CHECK: lis r3, 1 -;CHECK: rlwinm r2, r2, 8, 0, 31 -;CHECK: ori r3, r3, 34524 -;CHECK: stwx r2, r1, r3 +;CHECK: mfcr r0 +;CHECK: lis r2, 1 +;CHECK: rlwinm r0, r0, 8, 0, 31 +;CHECK: ori r2, r2, 34524 +;CHECK: stwx r0, r1, r2 ; Make sure that the register scavenger returns the same temporary register. -;CHECK: mfcr r2 -;CHECK: lis r3, 1 -;CHECK: rlwinm r2, r2, 12, 0, 31 -;CHECK: ori r3, r3, 34520 -;CHECK: stwx r2, r1, r3 +;CHECK: lis r2, 1 +;CHECK: mfcr r0 +;CHECK: ori r2, r2, 34520 +;CHECK: rlwinm r0, r0, 12, 0, 31 +;CHECK: stwx r0, r1, r2 %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %x1 = bitcast [100000 x i8]* %x to i8* ; [#uses=1] @@ -25,11 +25,11 @@ entry: br label %return return: ; preds = %entry -;CHECK: lis r3, 1 -;CHECK: ori r3, r3, 34524 -;CHECK: lwzx r2, r1, r3 -;CHECK: rlwinm r2, r2, 24, 0, 31 -;CHECK: mtcrf 32, r2 +;CHECK: lis r2, 1 +;CHECK: ori r2, r2, 34524 +;CHECK: lwzx r0, r1, r2 +;CHECK: rlwinm r0, r0, 24, 0, 31 +;CHECK: mtcrf 32, r0 ret void } -- cgit v1.2.3-18-g5258 From 0cfb42adb5072fb19a01dba3ea58a33fd5927947 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Fri, 15 Mar 2013 05:06:04 +0000 Subject: Allocate the RS spill slot for any PPC function with spills and a large stack frame For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'test/CodeGen/PowerPC/2010-02-12-saveCR.ll') diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 433fe5cc2a..0da6e4351b 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -9,12 +9,12 @@ entry: ;CHECK: mfcr r0 ;CHECK: lis r2, 1 ;CHECK: rlwinm r0, r0, 8, 0, 31 -;CHECK: ori r2, r2, 34524 +;CHECK: ori r2, r2, 34540 ;CHECK: stwx r0, r1, r2 ; Make sure that the register scavenger returns the same temporary register. ;CHECK: lis r2, 1 ;CHECK: mfcr r0 -;CHECK: ori r2, r2, 34520 +;CHECK: ori r2, r2, 34536 ;CHECK: rlwinm r0, r0, 12, 0, 31 ;CHECK: stwx r0, r1, r2 %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] @@ -26,7 +26,7 @@ entry: return: ; preds = %entry ;CHECK: lis r2, 1 -;CHECK: ori r2, r2, 34524 +;CHECK: ori r2, r2, 34540 ;CHECK: lwzx r0, r1, r2 ;CHECK: rlwinm r0, r0, 24, 0, 31 ;CHECK: mtcrf 32, r0 -- cgit v1.2.3-18-g5258 From 01f99d29c3010f2891e5edb78182216214017063 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Tue, 26 Mar 2013 18:57:22 +0000 Subject: Use multiple virtual registers in PPC CR spilling Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 40 ++++++++++++++++++------------- 1 file changed, 23 insertions(+), 17 deletions(-) (limited to 'test/CodeGen/PowerPC/2010-02-12-saveCR.ll') diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 0da6e4351b..79e8f96b39 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -2,21 +2,22 @@ ; ModuleID = 'hh.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" target triple = "powerpc-apple-darwin9.6" -; This formerly used R0 for both the stack address and CR. define void @foo() nounwind { entry: -;CHECK: mfcr r0 -;CHECK: lis r2, 1 -;CHECK: rlwinm r0, r0, 8, 0, 31 -;CHECK: ori r2, r2, 34540 -;CHECK: stwx r0, r1, r2 -; Make sure that the register scavenger returns the same temporary register. -;CHECK: lis r2, 1 -;CHECK: mfcr r0 -;CHECK: ori r2, r2, 34536 -;CHECK: rlwinm r0, r0, 12, 0, 31 -;CHECK: stwx r0, r1, r2 +; Note that part of what is being checked here is proper register reuse. +; CHECK: mfcr [[T1:r[0-9]+]] ; cr2 +; CHECK: lis [[T2:r[0-9]+]], 1 +; FIXME: There should only be one lis needed here! +; CHECK: lis [[T3:r[0-9]+]], 1 +; CHECK: addi r3, r1, 72 +; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31 +; CHECK: ori [[T2]], [[T2]], 34540 +; CHECK: ori [[T3]], [[T3]], 34536 +; CHECK: stwx [[T1]], r1, [[T2]] +; CHECK: mfcr [[T4:r[0-9]+]] ; cr3 +; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31 +; CHECK: stwx r4, r1, [[T3]] %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %x1 = bitcast [100000 x i8]* %x to i8* ; [#uses=1] @@ -25,11 +26,16 @@ entry: br label %return return: ; preds = %entry -;CHECK: lis r2, 1 -;CHECK: ori r2, r2, 34540 -;CHECK: lwzx r0, r1, r2 -;CHECK: rlwinm r0, r0, 24, 0, 31 -;CHECK: mtcrf 32, r0 +; CHECK: lis [[T1:r[0-9]+]], 1 +; CHECK: ori [[T1]], [[T1]], 34536 +; CHECK: lwzx [[T1]], r1, [[T1]] +; CHECK: rlwinm [[T1]], [[T1]], 20, 0, 31 +; CHECK: mtcrf 16, [[T1]] +; CHECK: lis [[T1]], 1 +; CHECK: ori [[T1]], [[T1]], 34540 +; CHECK: lwzx [[T1]], r1, [[T1]] +; CHECK: rlwinm [[T1]], [[T1]], 24, 0, 31 +; CHECK: mtcrf 32, [[T1]] ret void } -- cgit v1.2.3-18-g5258 From d957f957eee12cf26a7160e6015f0a7c2629904f Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Thu, 28 Mar 2013 03:38:16 +0000 Subject: Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructions There were a few places where kill flags were not being set correctly, and where 32-bit instruction variants were being used with 64-bit registers. After r178180, this code was being triggered causing llc to assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178220 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'test/CodeGen/PowerPC/2010-02-12-saveCR.ll') diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 79e8f96b39..097611a761 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -8,16 +8,15 @@ entry: ; Note that part of what is being checked here is proper register reuse. ; CHECK: mfcr [[T1:r[0-9]+]] ; cr2 ; CHECK: lis [[T2:r[0-9]+]], 1 -; FIXME: There should only be one lis needed here! -; CHECK: lis [[T3:r[0-9]+]], 1 ; CHECK: addi r3, r1, 72 ; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31 ; CHECK: ori [[T2]], [[T2]], 34540 -; CHECK: ori [[T3]], [[T3]], 34536 ; CHECK: stwx [[T1]], r1, [[T2]] +; CHECK: lis [[T3:r[0-9]+]], 1 ; CHECK: mfcr [[T4:r[0-9]+]] ; cr3 +; CHECK: ori [[T3]], [[T3]], 34536 ; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31 -; CHECK: stwx r4, r1, [[T3]] +; CHECK: stwx [[T4]], r1, [[T3]] %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %x1 = bitcast [100000 x i8]* %x to i8* ; [#uses=1] -- cgit v1.2.3-18-g5258