From c6b018b7379f4e1bcc4166a07b17d08180ed776d Mon Sep 17 00:00:00 2001
From: Eli Friedman <eli.friedman@gmail.com>
Date: Wed, 9 Mar 2011 01:28:35 +0000
Subject: PR9346: Prevent SimplifyDemandedBits from incorrectly introducing
 INT_MIN % -1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127306 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp')

diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index b12d4c3687..6e727ce6e3 100644
--- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -684,6 +684,10 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
     break;
   case Instruction::SRem:
     if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) {
+      // X % -1 demands all the bits because we don't want to introduce
+      // INT_MIN % -1 (== undef) by accident.
+      if (Rem->isAllOnesValue())
+        break;
       APInt RA = Rem->getValue().abs();
       if (RA.isPowerOf2()) {
         if (DemandedMask.ult(RA))    // srem won't affect demanded bits
-- 
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