From 675eb3b9ac547119f6db676ebdd172d40a797b1c Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Tue, 26 Mar 2013 17:47:11 +0000 Subject: Add PREFETCHW codegen support - Add 'PRFCHW' feature defined in AVX2 ISA extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86Subtarget.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'lib/Target/X86/X86Subtarget.h') diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index e97da4b6f4..b9f29fdcee 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -124,6 +124,9 @@ protected: /// HasADX - Processor has ADX instructions. bool HasADX; + /// HasPRFCHW - Processor has PRFCHW instructions. + bool HasPRFCHW; + /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. bool IsBTMemSlow; @@ -254,6 +257,7 @@ public: bool hasBMI2() const { return HasBMI2; } bool hasRTM() const { return HasRTM; } bool hasADX() const { return HasADX; } + bool hasPRFCHW() const { return HasPRFCHW; } bool isBTMemSlow() const { return IsBTMemSlow; } bool isUnalignedMemAccessFast() const { return IsUAMemFast; } bool hasVectorUAMem() const { return HasVectorUAMem; } -- cgit v1.2.3-18-g5258 From 0ca1a7f177ffd29c0af49f23cc7bd5f0b56a60d0 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Tue, 26 Mar 2013 22:46:02 +0000 Subject: Add HLE target feature git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178082 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86Subtarget.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'lib/Target/X86/X86Subtarget.h') diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index b9f29fdcee..108ef0eb1c 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -121,6 +121,9 @@ protected: /// HasRTM - Processor has RTM instructions. bool HasRTM; + /// HasHLE - Processor has HLE. + bool HasHLE; + /// HasADX - Processor has ADX instructions. bool HasADX; @@ -256,6 +259,7 @@ public: bool hasBMI() const { return HasBMI; } bool hasBMI2() const { return HasBMI2; } bool hasRTM() const { return HasRTM; } + bool hasHLE() const { return HasHLE; } bool hasADX() const { return HasADX; } bool hasPRFCHW() const { return HasPRFCHW; } bool isBTMemSlow() const { return IsBTMemSlow; } -- cgit v1.2.3-18-g5258 From 1edadea42f6f5c393b4fdb9d7ce1cf7eb9c24ab4 Mon Sep 17 00:00:00 2001 From: Preston Gurd Date: Wed, 27 Mar 2013 19:14:02 +0000 Subject: For the current Atom processor, the fastest way to handle a call indirect through a memory address is to load the memory address into a register and then call indirect through the register. This patch implements this improvement by modifying SelectionDAG to force a function address which is a memory reference to be loaded into a virtual register. Patch by Sriram Murali. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86Subtarget.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'lib/Target/X86/X86Subtarget.h') diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index 108ef0eb1c..cac3f579b0 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -159,6 +159,10 @@ protected: /// a stall when returning too early. bool PadShortFunctions; + /// CallRegIndirect - True if the Calls with memory reference should be converted + /// to a register-based indirect call. + bool CallRegIndirect; + /// stackAlignment - The minimum alignment known to hold of the stack frame on /// entry to the function and which must be maintained by every function. unsigned stackAlignment; @@ -269,6 +273,7 @@ public: bool useLeaForSP() const { return UseLeaForSP; } bool hasSlowDivide() const { return HasSlowDivide; } bool padShortFunctions() const { return PadShortFunctions; } + bool callRegIndirect() const { return CallRegIndirect; } bool isAtom() const { return X86ProcFamily == IntelAtom; } -- cgit v1.2.3-18-g5258 From c26392aa5d9c2dbca2909d6874d181455f8aeb8f Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Thu, 28 Mar 2013 23:41:26 +0000 Subject: Add support of RDSEED defined in AVX2 extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86Subtarget.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'lib/Target/X86/X86Subtarget.h') diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index cac3f579b0..6fbdb1d5f0 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -130,6 +130,9 @@ protected: /// HasPRFCHW - Processor has PRFCHW instructions. bool HasPRFCHW; + /// HasRDSEED - Processor has RDSEED instructions. + bool HasRDSEED; + /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. bool IsBTMemSlow; @@ -266,6 +269,7 @@ public: bool hasHLE() const { return HasHLE; } bool hasADX() const { return HasADX; } bool hasPRFCHW() const { return HasPRFCHW; } + bool hasRDSEED() const { return HasRDSEED; } bool isBTMemSlow() const { return IsBTMemSlow; } bool isUnalignedMemAccessFast() const { return IsUAMemFast; } bool hasVectorUAMem() const { return HasVectorUAMem; } -- cgit v1.2.3-18-g5258