From fed4d19eddcedf2a210a0ff3a290f4bf70927452 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sat, 10 Dec 2011 04:50:53 +0000 Subject: Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCRegisterInfo.cpp | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp') diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 3a69f9da28..27f7f4a1d7 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -464,12 +464,16 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); DebugLoc dl = MI.getDebugLoc(); - const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; - const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; - const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; - unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); - unsigned SrcReg = MI.getOperand(0).getReg(); + // FIXME: Once LLVM supports creating virtual registers here, or the register + // scavenger can return multiple registers, stop using reserved registers + // here. + (void) SPAdj; + (void) RS; + bool LP64 = Subtarget.isPPC64(); + unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : + (LP64 ? PPC::X0 : PPC::R0); + unsigned SrcReg = MI.getOperand(0).getReg(); // We need to store the CR in the low 4-bits of the saved value. First, issue // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. @@ -503,14 +507,18 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); DebugLoc dl = MI.getDebugLoc(); - const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; - const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; - const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; - unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); + // FIXME: Once LLVM supports creating virtual registers here, or the register + // scavenger can return multiple registers, stop using reserved registers + // here. + (void) SPAdj; + (void) RS; + + bool LP64 = Subtarget.isPPC64(); + unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : + (LP64 ? PPC::X0 : PPC::R0); unsigned DestReg = MI.getOperand(0).getReg(); assert(MI.definesRegister(DestReg) && "RESTORE_CR does not define its destination"); - bool LP64 = Subtarget.isPPC64(); addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), Reg), FrameIndex); -- cgit v1.2.3-70-g09d2