From 7d34267df63e23be1957f738de783c145febb7af Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 12 Dec 2012 01:32:07 +0000 Subject: - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term. Also added more comments to explain why it is generally ok to return true. - Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to be true for loaded source (memcpy) or zero constants (memset). The poor name choice is probably some kind of legacy issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 4b318dc16f..46986613cb 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -362,7 +362,7 @@ namespace llvm { virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, - unsigned SrcAlign, bool IsZeroVal, + unsigned SrcAlign, bool ZeroOrLdSrc, bool MemcpyStrSrc, MachineFunction &MF) const; -- cgit v1.2.3-18-g5258 From 946a3a9f22c967d5432eaab5fa464b91343477cd Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 12 Dec 2012 02:34:41 +0000 Subject: Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 46986613cb..ff25df94e3 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -362,7 +362,8 @@ namespace llvm { virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, - unsigned SrcAlign, bool ZeroOrLdSrc, + unsigned SrcAlign, + bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const; -- cgit v1.2.3-18-g5258 From ed23fa8e55f5a58741c20c601410c2822d00f066 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Sat, 15 Dec 2012 00:20:05 +0000 Subject: This code implements most of mips16 hardfloat as it is done by gcc. In this case, essentially it is soft float with different library routines. The next step will be to make this fully interoperational with mips32 floating point and that requires creating stubs for functions with signatures that contain floating point types. I have a more sophisticated design for mips16 hardfloat which I hope to implement at a later time that directly does floating point without the need for function calls. The mips16 encoding has no floating point instructions so one needs to switch to mips32 mode to execute floating point instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170259 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index ff25df94e3..c4b38c66ee 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -174,6 +174,8 @@ namespace llvm { virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; private: + void setMips16HardFloatLibCalls(); + /// ByValArgInfo - Byval argument information. struct ByValArgInfo { unsigned FirstIdx; // Index of the first register used. -- cgit v1.2.3-18-g5258 From bf6a77b98715012c0fa3bdbb3ba55fa7c24c1548 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 22 Jan 2013 20:05:56 +0000 Subject: [mips] Clean up code in MipsTargetLowering::LowerCall. No functional change intended git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173189 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index c4b38c66ee..deb6ad0463 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -20,6 +20,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Target/TargetLowering.h" +#include namespace llvm { namespace MipsISD { @@ -294,7 +295,7 @@ namespace llvm { /// passByValArg - Pass a byval argument in registers or on stack. void passByValArg(SDValue Chain, DebugLoc DL, - SmallVector, 16> &RegsToPass, + std::deque< std::pair > &RegsToPass, SmallVector &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const MipsCC &CC, const ByValArgInfo &ByVal, -- cgit v1.2.3-18-g5258 From 8453b3f66a3c3200ea828491ef5cf162db9ccfb2 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Thu, 24 Jan 2013 04:24:02 +0000 Subject: The next phase of Mips16 hard float implementation. Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173320 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index deb6ad0463..c682c89f87 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -21,6 +21,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Target/TargetLowering.h" #include +#include namespace llvm { namespace MipsISD { @@ -177,6 +178,12 @@ namespace llvm { void setMips16HardFloatLibCalls(); + unsigned int + getMips16HelperFunctionStubNumber(ArgListTy &Args) const; + + const char *getMips16HelperFunction + (Type* RetTy, ArgListTy &Args, bool &needHelper) const; + /// ByValArgInfo - Byval argument information. struct ByValArgInfo { unsigned FirstIdx; // Index of the first register used. -- cgit v1.2.3-18-g5258 From bc49cf73079c1223fba5046047517fc3c00d5284 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Mon, 28 Jan 2013 02:46:49 +0000 Subject: Make some code a little simpler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173649 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index c682c89f87..053f8defc7 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -176,6 +176,8 @@ namespace llvm { virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; private: + void SetMips16LibcallName(RTLIB::Libcall, const char *Name); + void setMips16HardFloatLibCalls(); unsigned int -- cgit v1.2.3-18-g5258 From 544cc21cf4807116251a699d8b1d3d4bace21597 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Wed, 30 Jan 2013 00:26:49 +0000 Subject: [mips] Lower EH_RETURN. Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173862 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 053f8defc7..00aa282530 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -65,6 +65,8 @@ namespace llvm { // Return Ret, + EH_RETURN, + // MAdd/Sub nodes MAdd, MAddu, @@ -275,6 +277,7 @@ namespace llvm { SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; -- cgit v1.2.3-18-g5258 From ffd28a44f04ab2de5a7092fbd5ff17af79f56e28 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Fri, 15 Feb 2013 21:45:11 +0000 Subject: [mips] Clean up class MipsCCInfo. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175310 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 48 +++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 22 deletions(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 00aa282530..3b4635553b 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -201,53 +201,57 @@ namespace llvm { /// arguments and inquire about calling convention information. class MipsCC { public: - MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32, - CCState &Info); + MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info); - void analyzeCallOperands(const SmallVectorImpl &Outs); + void analyzeCallOperands(const SmallVectorImpl &Outs, + bool IsVarArg); void analyzeFormalArguments(const SmallVectorImpl &Ins); - void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, - CCValAssign::LocInfo LocInfo, - ISD::ArgFlagsTy ArgFlags); - const CCState &getCCInfo() const { return CCInfo; } /// hasByValArg - Returns true if function has byval arguments. bool hasByValArg() const { return !ByValArgs.empty(); } - /// useRegsForByval - Returns true if the calling convention allows the - /// use of registers to pass byval arguments. - bool useRegsForByval() const { return UseRegsForByval; } - /// regSize - Size (in number of bits) of integer registers. - unsigned regSize() const { return RegSize; } + unsigned regSize() const { return IsO32 ? 4 : 8; } /// numIntArgRegs - Number of integer registers available for calls. - unsigned numIntArgRegs() const { return NumIntArgRegs; } + unsigned numIntArgRegs() const; /// reservedArgArea - The size of the area the caller reserves for /// register arguments. This is 16-byte if ABI is O32. - unsigned reservedArgArea() const { return ReservedArgArea; } + unsigned reservedArgArea() const; - /// intArgRegs - Pointer to array of integer registers. - const uint16_t *intArgRegs() const { return IntArgRegs; } + /// Return pointer to array of integer argument registers. + const uint16_t *intArgRegs() const; typedef SmallVector::const_iterator byval_iterator; byval_iterator byval_begin() const { return ByValArgs.begin(); } byval_iterator byval_end() const { return ByValArgs.end(); } private: + void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags); + + /// useRegsForByval - Returns true if the calling convention allows the + /// use of registers to pass byval arguments. + bool useRegsForByval() const { return CallConv != CallingConv::Fast; } + + /// Return the function that analyzes fixed argument list functions. + llvm::CCAssignFn *fixedArgFn() const; + + /// Return the function that analyzes variable argument list functions. + llvm::CCAssignFn *varArgFn() const; + + const uint16_t *shadowRegs() const; + void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, unsigned Align); CCState &CCInfo; - bool UseRegsForByval; - unsigned RegSize; - unsigned NumIntArgRegs; - unsigned ReservedArgArea; - const uint16_t *IntArgRegs, *ShadowRegs; + CallingConv::ID CallConv; + bool IsO32; SmallVector ByValArgs; - llvm::CCAssignFn *FixedFn, *VarFn; }; // Subtarget Info -- cgit v1.2.3-18-g5258 From ffbe432595c78ba28c8a9d200bf92996eed5e5d9 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Thu, 21 Feb 2013 04:22:38 +0000 Subject: Expand the sel pseudo/macro. This generates basic blocks where previously there were inline br .+4 instructions. Soon everything can enjoy the full instruction scheduling experience. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175718 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 3b4635553b..2531a20b0f 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -404,6 +404,9 @@ namespace llvm { MachineBasicBlock *BB, unsigned Size) const; MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size) const; + MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI, + MachineBasicBlock *BB) const; + }; } -- cgit v1.2.3-18-g5258 From 7617d032ae12ba96ad65f37d91274e6f8c14e690 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Fri, 22 Feb 2013 05:10:51 +0000 Subject: Expand mips16 SelT form pseudso/macros. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175862 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 2531a20b0f..834391536a 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -406,6 +406,9 @@ namespace llvm { MachineBasicBlock *BB, unsigned Size) const; MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2, + MachineInstr *MI, + MachineBasicBlock *BB) const; }; } -- cgit v1.2.3-18-g5258 From 00ddc5a7274fb4131f1a724bc350fd756156a80f Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Fri, 22 Feb 2013 05:59:39 +0000 Subject: Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refers to the immediate operand of sli or cmp function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175865 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 834391536a..789456a5af 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -406,7 +406,7 @@ namespace llvm { MachineBasicBlock *BB, unsigned Size) const; MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2, + MachineBasicBlock *EmitSeliT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, MachineBasicBlock *BB) const; -- cgit v1.2.3-18-g5258 From 50354a3f4a5c9e3689d502a935430f2a57a44af2 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Sat, 23 Feb 2013 03:09:56 +0000 Subject: Expand pseudos/macros for Selt. This is the last of the complex macros.The rest is some small misc. stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 789456a5af..2896de5d57 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -410,6 +410,9 @@ namespace llvm { MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2, + MachineInstr *MI, + MachineBasicBlock *BB) const; }; } -- cgit v1.2.3-18-g5258 From 459d35cb7975804048684261f2358eedbd2209c1 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Sun, 24 Feb 2013 06:16:39 +0000 Subject: Make psuedo FEXT_T8I816_ins a custom inserter. It should be expanded as early as possible; which means during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175984 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 2896de5d57..ac05c83210 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -413,6 +413,9 @@ namespace llvm { MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, + MachineInstr *MI, + MachineBasicBlock *BB) const; }; } -- cgit v1.2.3-18-g5258 From 29cb2591f9f7ec948e7b0e719b1db6cef99010d0 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Sun, 24 Feb 2013 23:17:51 +0000 Subject: Make psuedo FEXT_T8I816_ins into a custom emitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176002 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index ac05c83210..2d1e9a95ea 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -416,6 +416,9 @@ namespace llvm { MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitFEXT_T8I8I16_ins( + unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, + MachineInstr *MI, MachineBasicBlock *BB) const; }; } -- cgit v1.2.3-18-g5258 From de89ecd011c453108c7641f44360f3a93af90206 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Mon, 25 Feb 2013 02:25:47 +0000 Subject: Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176007 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 2d1e9a95ea..f0f37824cb 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -419,6 +419,13 @@ namespace llvm { MachineBasicBlock *EmitFEXT_T8I8I16_ins( unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitFEXT_CCRX16_ins( + unsigned SltOpc, + MachineInstr *MI, MachineBasicBlock *BB) const; + MachineBasicBlock *EmitFEXT_CCRXI16_ins( + unsigned SltiOpc, unsigned SltiXOpc, + MachineInstr *MI, MachineBasicBlock *BB )const; + }; } -- cgit v1.2.3-18-g5258 From a6b20ced765b67a85d9219d0c8547fc9c133e14f Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Fri, 1 Mar 2013 18:40:30 +0000 Subject: Fix PR10475 - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index f0f37824cb..5b2ef08b7b 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -151,7 +151,7 @@ namespace llvm { public: explicit MipsTargetLowering(MipsTargetMachine &TM); - virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } + virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const; -- cgit v1.2.3-18-g5258 From 5fdee6d2b5a72a826bf6db47c319ddac08cd9f57 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 5 Mar 2013 22:13:04 +0000 Subject: [mips] Correct handling of fp128 (long double) formals and read long double parameters from floating point registers if target is mips64 hard float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176520 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 5b2ef08b7b..22751694bb 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -19,6 +19,7 @@ #include "MipsSubtarget.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/IR/Function.h" #include "llvm/Target/TargetLowering.h" #include #include @@ -205,7 +206,9 @@ namespace llvm { void analyzeCallOperands(const SmallVectorImpl &Outs, bool IsVarArg); - void analyzeFormalArguments(const SmallVectorImpl &Ins); + void analyzeFormalArguments(const SmallVectorImpl &Ins, + bool IsSoftFloat, + Function::const_arg_iterator FuncArg); const CCState &getCCInfo() const { return CCInfo; } /// hasByValArg - Returns true if function has byval arguments. @@ -248,6 +251,13 @@ namespace llvm { void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, unsigned Align); + /// Return the type of the register which is used to pass an argument or + /// return a value. This function returns f64 if the argument is an i64 + /// value which has been generated as a result of softening an f128 value. + /// Otherwise, it just returns VT. + MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, + bool IsSoftFloat) const; + CCState &CCInfo; CallingConv::ID CallConv; bool IsO32; -- cgit v1.2.3-18-g5258 From cb2eafdfa358ae8a1e1f9ae39d8c72cd4d446da1 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 5 Mar 2013 22:20:28 +0000 Subject: [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating point registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176521 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 22751694bb..ee40232ca6 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -205,7 +205,9 @@ namespace llvm { MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info); void analyzeCallOperands(const SmallVectorImpl &Outs, - bool IsVarArg); + bool IsVarArg, bool IsSoftFloat, + const SDNode *CallNode, + std::vector &FuncArgs); void analyzeFormalArguments(const SmallVectorImpl &Ins, bool IsSoftFloat, Function::const_arg_iterator FuncArg); -- cgit v1.2.3-18-g5258 From 7433b2e1142a46c1dbb491d91e0175cb9ce83167 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 5 Mar 2013 22:41:55 +0000 Subject: [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly handle fp128 returns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index ee40232ca6..4424521f5f 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -211,6 +211,14 @@ namespace llvm { void analyzeFormalArguments(const SmallVectorImpl &Ins, bool IsSoftFloat, Function::const_arg_iterator FuncArg); + + void analyzeCallResult(const SmallVectorImpl &Ins, + bool IsSoftFloat, const SDNode *CallNode, + const Type *RetTy) const; + + void analyzeReturn(const SmallVectorImpl &Outs, + bool IsSoftFloat, const Type *RetTy) const; + const CCState &getCCInfo() const { return CCInfo; } /// hasByValArg - Returns true if function has byval arguments. @@ -260,6 +268,10 @@ namespace llvm { MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, bool IsSoftFloat) const; + template + void analyzeReturn(const SmallVectorImpl &RetVals, bool IsSoftFloat, + const SDNode *CallNode, const Type *RetTy) const; + CCState &CCInfo; CallingConv::ID CallConv; bool IsO32; @@ -276,7 +288,8 @@ namespace llvm { CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl &Ins, DebugLoc dl, SelectionDAG &DAG, - SmallVectorImpl &InVals) const; + SmallVectorImpl &InVals, + const SDNode *CallNode, const Type *RetTy) const; // Lower Operand specifics SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; -- cgit v1.2.3-18-g5258 From b7656a9cc4bf36752df38e7c02b910c9390b9c39 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Wed, 6 Mar 2013 21:32:03 +0000 Subject: [mips] Custom-legalize BR_JT. In N64-static, GOT address is needed to compute the branch address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176580 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 1 + 1 file changed, 1 insertion(+) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 4424521f5f..02d7e2ffcf 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -292,6 +292,7 @@ namespace llvm { const SDNode *CallNode, const Type *RetTy) const; // Lower Operand specifics + SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; -- cgit v1.2.3-18-g5258 From f635ef401786c84df32090251a8cf45981ecca33 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 12 Mar 2013 00:16:36 +0000 Subject: [mips] Rename function and variable names to start with proper case. Fix typos. Delete commented-out code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176844 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.h | 80 +++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 40 deletions(-) (limited to 'lib/Target/Mips/MipsISelLowering.h') diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 02d7e2ffcf..de925e16ab 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -179,7 +179,7 @@ namespace llvm { virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; private: - void SetMips16LibcallName(RTLIB::Libcall, const char *Name); + void setMips16LibcallName(RTLIB::Libcall, const char *Name); void setMips16HardFloatLibCalls(); @@ -292,36 +292,36 @@ namespace llvm { const SDNode *CallNode, const Type *RetTy) const; // Lower Operand specifics - SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; - SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; - SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; - SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG, + SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; + SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; + SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; + SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, bool IsSRA) const; - SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; - /// IsEligibleForTailCallOptimization - Check whether the call is eligible + /// isEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. - bool IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, + bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, unsigned NextStackOffset, const MipsFunctionInfo& FI) const; @@ -419,36 +419,36 @@ namespace llvm { virtual unsigned getJumpTableEncoding() const; - MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI, + MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, + MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, bool Nand = false) const; - MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI, + MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, bool Nand = false) const; - MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, + MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size) const; - MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI, + MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size) const; - MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI, + MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitSeliT16(unsigned Opc1, unsigned Opc2, + MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2, + MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, + MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitFEXT_T8I8I16_ins( + MachineBasicBlock *emitFEXT_T8I8I16_ins( unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitFEXT_CCRX16_ins( + MachineBasicBlock *emitFEXT_CCRX16_ins( unsigned SltOpc, MachineInstr *MI, MachineBasicBlock *BB) const; - MachineBasicBlock *EmitFEXT_CCRXI16_ins( + MachineBasicBlock *emitFEXT_CCRXI16_ins( unsigned SltiOpc, unsigned SltiXOpc, MachineInstr *MI, MachineBasicBlock *BB )const; -- cgit v1.2.3-18-g5258