From 759e3fa641d0ad01012d16d913015c9f69c8d2ab Mon Sep 17 00:00:00 2001 From: Roman Divacky Date: Wed, 19 Dec 2012 19:55:47 +0000 Subject: Remove edis - the enhanced disassembler. Fixes PR14654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 099a1e79a5..9560f3fc52 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -14,7 +14,6 @@ #include "Mips.h" #include "MipsRegisterInfo.h" #include "MipsSubtarget.h" -#include "llvm/MC/EDInstInfo.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" @@ -23,9 +22,6 @@ #include "llvm/Support/MemoryObject.h" #include "llvm/Support/TargetRegistry.h" -// Not a normal header, this must come last. -#include "MipsGenEDInfo.inc" - using namespace llvm; typedef MCDisassembler::DecodeStatus DecodeStatus; @@ -43,9 +39,6 @@ public: virtual ~MipsDisassemblerBase() {} - /// getEDInfo - See MCDisassembler. - const EDInstInfo *getEDInfo() const; - const MCRegisterInfo *getRegInfo() const { return RegInfo; } private: @@ -93,10 +86,6 @@ public: } // end anonymous namespace -const EDInstInfo *MipsDisassemblerBase::getEDInfo() const { - return instInfoMips; -} - // Forward declare these because the autogenerated code will reference them. // Definitions are further down. static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, -- cgit v1.2.3-70-g09d2 From edaf85606d7ac8368dd7fa0e9fd4042e523a6e3a Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Sat, 12 Jan 2013 15:37:00 +0000 Subject: MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a warning. [-Wunused-function] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172319 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 9560f3fc52..1efeffd328 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -128,11 +128,6 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); - static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -459,17 +454,6 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, return MCDisassembler::Success; } -static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { - //Currently only hardware register 29 is supported - if (RegNo != 29) - return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); - return MCDisassembler::Success; -} - static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, -- cgit v1.2.3-70-g09d2 From 490c7d97737ea7719efcea7321d3cfa3984b0027 Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Wed, 16 Jan 2013 00:07:45 +0000 Subject: Akira, Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 5 ++++- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 16 ++++++++++++++++ lib/Target/Mips/MipsRegisterInfo.td | 2 +- test/MC/Disassembler/Mips/mips32.txt | 6 ++++++ test/MC/Disassembler/Mips/mips32_le.txt | 6 ++++++ test/MC/Mips/mips-alu-instructions.s | 5 +++++ test/MC/Mips/mips64-alu-instructions.s | 6 ++++++ 7 files changed, 44 insertions(+), 2 deletions(-) (limited to 'lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 57338df53c..482210673a 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1071,6 +1071,9 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl &Operands) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseHW64Regs(SmallVectorImpl &Operands) { + + if (!isMips64()) + return MatchOperand_NoMatch; //if the first token is not '$' we have error if (Parser.getTok().isNot(AsmToken::Dollar)) return MatchOperand_NoMatch; @@ -1088,7 +1091,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl &Operands) { MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S, Parser.getTok().getLoc()); - op->setRegKind(MipsOperand::Kind_HWRegs); + op->setRegKind(MipsOperand::Kind_HW64Regs); Operands.push_back(op); Parser.Lex(); // Eat reg number diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 1efeffd328..9560f3fc52 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -128,6 +128,11 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -454,6 +459,17 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + //Currently only hardware register 29 is supported + if (RegNo != 29) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index c6eb0e1e87..f93dd86c17 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand { let ParserMatchClass = HWRegsAsmOperand; } -def HW64RegsOpnd : RegisterOperand { +def HW64RegsOpnd : RegisterOperand { let ParserMatchClass = HW64RegsAsmOperand; } diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index a1933190b1..70224860bc 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x7c 0x05 0xe8 0x3b diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 08b36726ba..48fa8e2c7f 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x3b 0xe8 0x05 0x7c diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index ee2a9a0db4..52fd900091 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -81,6 +81,10 @@ # CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00] # CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00] # CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] add $9,$6,$7 add $9,$6,17767 addu $9,$6,-15001 @@ -98,3 +102,4 @@ neg $6,$7 negu $6,$7 move $7,$8 + rdhwr $5, $29 diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index a77ed43ff1..d30ddeee71 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -78,6 +78,11 @@ # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] # CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] # CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] + dadd $9,$6,$7 dadd $9,$6,17767 daddu $9,$6,-15001 @@ -92,3 +97,4 @@ multu $3,$5 dsubu $4,$3,$5 move $7,$8 + rdhwr $5, $29 -- cgit v1.2.3-70-g09d2 From 457ee1a12e2c52624af7fdb81cf938f6d8d96572 Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Wed, 16 Jan 2013 01:29:10 +0000 Subject: reverting 172579 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 5 +---- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 16 ---------------- lib/Target/Mips/MipsRegisterInfo.td | 2 +- test/MC/Disassembler/Mips/mips32.txt | 6 ------ test/MC/Disassembler/Mips/mips32_le.txt | 6 ------ test/MC/Mips/mips-alu-instructions.s | 5 ----- test/MC/Mips/mips64-alu-instructions.s | 6 ------ 7 files changed, 2 insertions(+), 44 deletions(-) (limited to 'lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 482210673a..57338df53c 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1071,9 +1071,6 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl &Operands) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseHW64Regs(SmallVectorImpl &Operands) { - - if (!isMips64()) - return MatchOperand_NoMatch; //if the first token is not '$' we have error if (Parser.getTok().isNot(AsmToken::Dollar)) return MatchOperand_NoMatch; @@ -1091,7 +1088,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl &Operands) { MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S, Parser.getTok().getLoc()); - op->setRegKind(MipsOperand::Kind_HW64Regs); + op->setRegKind(MipsOperand::Kind_HWRegs); Operands.push_back(op); Parser.Lex(); // Eat reg number diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 9560f3fc52..1efeffd328 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -128,11 +128,6 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); - static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -459,17 +454,6 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, return MCDisassembler::Success; } -static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { - //Currently only hardware register 29 is supported - if (RegNo != 29) - return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); - return MCDisassembler::Success; -} - static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index f93dd86c17..c6eb0e1e87 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand { let ParserMatchClass = HWRegsAsmOperand; } -def HW64RegsOpnd : RegisterOperand { +def HW64RegsOpnd : RegisterOperand { let ParserMatchClass = HW64RegsAsmOperand; } diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index 70224860bc..a1933190b1 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -404,9 +404,3 @@ # CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 - -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop -0x7c 0x05 0xe8 0x3b diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 48fa8e2c7f..08b36726ba 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -404,9 +404,3 @@ # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 - -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop -0x3b 0xe8 0x05 0x7c diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index 52fd900091..ee2a9a0db4 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -81,10 +81,6 @@ # CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00] # CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00] # CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01] -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] add $9,$6,$7 add $9,$6,17767 addu $9,$6,-15001 @@ -102,4 +98,3 @@ neg $6,$7 negu $6,$7 move $7,$8 - rdhwr $5, $29 diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index d30ddeee71..a77ed43ff1 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -78,11 +78,6 @@ # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] # CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] # CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01] -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] - dadd $9,$6,$7 dadd $9,$6,17767 daddu $9,$6,-15001 @@ -97,4 +92,3 @@ multu $3,$5 dsubu $4,$3,$5 move $7,$8 - rdhwr $5, $29 -- cgit v1.2.3-70-g09d2 From c147b678206db510336ee95c3b55dc9c0ff19595 Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Thu, 17 Jan 2013 00:28:20 +0000 Subject: This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 8 +++++++- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 16 ++++++++++++++++ lib/Target/Mips/MipsRegisterInfo.td | 2 +- test/MC/Disassembler/Mips/mips32.txt | 6 ++++++ test/MC/Disassembler/Mips/mips32_le.txt | 6 ++++++ test/MC/Mips/mips-alu-instructions.s | 5 +++++ test/MC/Mips/mips64-alu-instructions.s | 6 ++++++ 7 files changed, 47 insertions(+), 2 deletions(-) (limited to 'lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 57338df53c..39a53aeba7 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1045,6 +1045,9 @@ MipsAsmParser::parseCPURegs(SmallVectorImpl &Operands) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseHWRegs(SmallVectorImpl &Operands) { + if (isMips64()) + return MatchOperand_NoMatch; + // if the first token is not '$' we have error if (Parser.getTok().isNot(AsmToken::Dollar)) return MatchOperand_NoMatch; @@ -1071,6 +1074,9 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl &Operands) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseHW64Regs(SmallVectorImpl &Operands) { + + if (!isMips64()) + return MatchOperand_NoMatch; //if the first token is not '$' we have error if (Parser.getTok().isNot(AsmToken::Dollar)) return MatchOperand_NoMatch; @@ -1088,7 +1094,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl &Operands) { MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S, Parser.getTok().getLoc()); - op->setRegKind(MipsOperand::Kind_HWRegs); + op->setRegKind(MipsOperand::Kind_HW64Regs); Operands.push_back(op); Parser.Lex(); // Eat reg number diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 1efeffd328..9560f3fc52 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -128,6 +128,11 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -454,6 +459,17 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + //Currently only hardware register 29 is supported + if (RegNo != 29) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index c6eb0e1e87..f93dd86c17 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand { let ParserMatchClass = HWRegsAsmOperand; } -def HW64RegsOpnd : RegisterOperand { +def HW64RegsOpnd : RegisterOperand { let ParserMatchClass = HW64RegsAsmOperand; } diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index a1933190b1..70224860bc 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x7c 0x05 0xe8 0x3b diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 08b36726ba..48fa8e2c7f 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -404,3 +404,9 @@ # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 + +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop +0x3b 0xe8 0x05 0x7c diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index ee2a9a0db4..52fd900091 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -81,6 +81,10 @@ # CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00] # CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00] # CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] add $9,$6,$7 add $9,$6,17767 addu $9,$6,-15001 @@ -98,3 +102,4 @@ neg $6,$7 negu $6,$7 move $7,$8 + rdhwr $5, $29 diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index a77ed43ff1..d30ddeee71 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -78,6 +78,11 @@ # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] # CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] # CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01] +# CHECK: .set push +# CHECK: .set mips32r2 +# CHECK: rdhwr $5, $29 +# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] + dadd $9,$6,$7 dadd $9,$6,17767 daddu $9,$6,-15001 @@ -92,3 +97,4 @@ multu $3,$5 dsubu $4,$3,$5 move $7,$8 + rdhwr $5, $29 -- cgit v1.2.3-70-g09d2 From 38f85c5b9f2e2a7e1364ce44b6b8cd1ec0ffb0b3 Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Thu, 14 Feb 2013 03:05:25 +0000 Subject: Remove the form field from Mips16 instruction formats and set things up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 14 +++ lib/Target/Mips/Mips16InstrFormats.td | 111 ++++++++-------------- lib/Target/Mips/Mips16InstrInfo.td | 35 ++++--- 3 files changed, 73 insertions(+), 87 deletions(-) (limited to 'lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 9560f3fc52..025a783f93 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -93,6 +93,11 @@ static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -322,6 +327,15 @@ static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); } +static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + + return MCDisassembler::Fail; + +} + static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, diff --git a/lib/Target/Mips/Mips16InstrFormats.td b/lib/Target/Mips/Mips16InstrFormats.td index 61602b62fb..4ff62ef3b6 100644 --- a/lib/Target/Mips/Mips16InstrFormats.td +++ b/lib/Target/Mips/Mips16InstrFormats.td @@ -29,45 +29,13 @@ // //===----------------------------------------------------------------------===// -// Format specifies the encoding used by the instruction. This is part of the -// ad-hoc solution used to emit machine instruction encodings by our machine -// code emitter. -// -class Format16 val> { - bits<5> Value = val; -} - -def Pseudo16 : Format16<0>; -def FrmI16 : Format16<1>; -def FrmRI16 : Format16<2>; -def FrmRR16 : Format16<3>; -def FrmRRI16 : Format16<4>; -def FrmRRR16 : Format16<5>; -def FrmRRI_A16 : Format16<6>; -def FrmSHIFT16 : Format16<7>; -def FrmI8_TYPE16 : Format16<8>; -def FrmI8_MOVR3216 : Format16<9>; -def FrmI8_MOV32R16 : Format16<10>; -def FrmI8_SVRS16 : Format16<11>; -def FrmJAL16 : Format16<12>; -def FrmJALX16 : Format16<13>; -def FrmEXT_I16 : Format16<14>; -def FrmASMACRO16 : Format16<15>; -def FrmEXT_RI16 : Format16<16>; -def FrmEXT_RRI16 : Format16<17>; -def FrmEXT_RRI_A16 : Format16<18>; -def FrmEXT_SHIFT16 : Format16<19>; -def FrmEXT_I816 : Format16<20>; -def FrmEXT_I8_SVRS16 : Format16<21>; -def FrmOther16 : Format16<22>; // Instruction w/ a custom format // Base class for Mips 16 Format // This class does not depend on the instruction size // class MipsInst16_Base pattern, - InstrItinClass itin, Format16 f>: Instruction + InstrItinClass itin>: Instruction { - Format16 Form = f; let Namespace = "Mips"; @@ -78,14 +46,6 @@ class MipsInst16_Base pattern, let Pattern = pattern; let Itinerary = itin; - // - // Attributes specific to Mips instructions... - // - bits<5> FormBits = Form.Value; - - // TSFlags layout should be kept in sync with MipsInstrInfo.h. - let TSFlags{4-0} = FormBits; - let Predicates = [InMips16Mode]; } @@ -93,30 +53,35 @@ class MipsInst16_Base pattern, // Generic Mips 16 Format // class MipsInst16 pattern, - InstrItinClass itin, Format16 f>: - MipsInst16_Base + InstrItinClass itin>: + MipsInst16_Base { field bits<16> Inst; bits<5> Opcode = 0; // Top 5 bits are the 'opcode' field let Inst{15-11} = Opcode; + + let Size=2; + field bits<16> SoftFail = 0; } // // For 32 bit extended instruction forms. // class MipsInst16_32 pattern, - InstrItinClass itin, Format16 f>: - MipsInst16_Base + InstrItinClass itin>: + MipsInst16_Base { field bits<32> Inst; - + + let Size=4; + field bits<32> SoftFail = 0; } class MipsInst16_EXTEND pattern, - InstrItinClass itin, Format16 f>: - MipsInst16_32 + InstrItinClass itin>: + MipsInst16_32 { let Inst{31-27} = 0b11110; } @@ -125,7 +90,7 @@ class MipsInst16_EXTEND pattern, // Mips Pseudo Instructions Format class MipsPseudo16 pattern>: - MipsInst16 { + MipsInst16 { let isCodeGenOnly = 1; let isPseudo = 1; } @@ -137,7 +102,7 @@ class MipsPseudo16 pattern>: class FI16 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<11> imm11; @@ -152,7 +117,7 @@ class FI16 op, dag outs, dag ins, string asmstr, list pattern, class FRI16 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<8> imm8; @@ -169,7 +134,7 @@ class FRI16 op, dag outs, dag ins, string asmstr, class FRR16 _funct, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; @@ -188,7 +153,7 @@ class FRR16 _funct, dag outs, dag ins, string asmstr, // class FRR_SF16 _funct, bits<3> _subfunct, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> subfunct; @@ -208,7 +173,7 @@ class FRR_SF16 _funct, bits<3> _subfunct, dag outs, dag ins, // class FC16 _funct, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<6> _code; // code is a keyword in tablegen bits<5> funct; @@ -226,7 +191,7 @@ class FC16 _funct, dag outs, dag ins, string asmstr, class FRR16_JALRC _nd, bits<1> _l, bits<1> r_a, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<1> nd; @@ -252,7 +217,7 @@ class FRR16_JALRC _nd, bits<1> _l, bits<1> r_a, class FRRI16 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; @@ -272,7 +237,7 @@ class FRRI16 op, dag outs, dag ins, string asmstr, class FRRR16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; @@ -294,7 +259,7 @@ class FRRR16 _f, dag outs, dag ins, string asmstr, class FRRI_A16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; @@ -316,7 +281,7 @@ class FRRI_A16 _f, dag outs, dag ins, string asmstr, class FSHIFT16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> rx; bits<3> ry; @@ -338,7 +303,7 @@ class FSHIFT16 _f, dag outs, dag ins, string asmstr, class FI816 _func, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> func; bits<8> imm8; @@ -356,7 +321,7 @@ class FI816 _func, dag outs, dag ins, string asmstr, class FI8_MOVR3216 pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<4> ry; @@ -378,7 +343,7 @@ class FI8_MOVR3216 pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<3> func; @@ -402,7 +367,7 @@ class FI8_MOV32R16 _s, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16 + MipsInst16 { bits<1> s; bits<1> ra = 0; @@ -429,7 +394,7 @@ class FI8_SVRS16 _s, dag outs, dag ins, string asmstr, class FJAL16 _X, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_32 + MipsInst16_32 { bits<1> X; bits<26> imm26; @@ -452,7 +417,7 @@ class FJAL16 _X, dag outs, dag ins, string asmstr, class FEXT_I16 _eop, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<16> imm16; bits<5> eop; @@ -474,7 +439,7 @@ class FEXT_I16 _eop, dag outs, dag ins, string asmstr, class FASMACRO16 pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<3> select; bits<3> p4; @@ -503,7 +468,7 @@ class FASMACRO16 _op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<16> imm16; bits<5> op; @@ -527,7 +492,7 @@ class FEXT_RI16 _op, dag outs, dag ins, string asmstr, class FEXT_RRI16 _op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<5> op; bits<16> imm16; @@ -552,7 +517,7 @@ class FEXT_RRI16 _op, dag outs, dag ins, string asmstr, class FEXT_RRI_A16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<15> imm15; bits<3> rx; @@ -578,7 +543,7 @@ class FEXT_RRI_A16 _f, dag outs, dag ins, string asmstr, class FEXT_SHIFT16 _f, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<6> sa6; bits<3> rx; @@ -605,7 +570,7 @@ class FEXT_SHIFT16 _f, dag outs, dag ins, string asmstr, class FEXT_I816 _funct, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<16> imm16; bits<5> I8; @@ -630,7 +595,7 @@ class FEXT_I816 _funct, dag outs, dag ins, string asmstr, class FEXT_I8_SVRS16 s_, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin>: - MipsInst16_EXTEND + MipsInst16_EXTEND { bits<3> xsregs =0; bits<8> framesize =0; @@ -659,5 +624,3 @@ class FEXT_I8_SVRS16 s_, dag outs, dag ins, string asmstr, } - - diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 06344dbccf..872de52f33 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -335,8 +335,7 @@ class FRRR16_ins _f, string asmstr, InstrItinClass itin> : class Sel f1, string op, InstrItinClass itin>: MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, CPU16Regs:$rt), - !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin, - Pseudo16> { + !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin> { let isCodeGenOnly=1; let Constraints = "$rd = $rd_"; } @@ -362,8 +361,7 @@ class SeliT f1, string op1, bits<5> f2, string op2, CPU16Regs:$rl, simm16:$imm), !strconcat(op2, !strconcat("\t$rl, $imm\n\t", - !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, - Pseudo16> { + !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin> { let isCodeGenOnly=1; let Constraints = "$rd = $rd_"; } @@ -386,8 +384,7 @@ class SelT f1, string op1, bits<5> f2, string op2, CPU16Regs:$rl, CPU16Regs:$rr), !strconcat(op2, !strconcat("\t$rl, $rr\n\t", - !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, - Pseudo16> { + !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin> { let isCodeGenOnly=1; let Constraints = "$rd = $rd_"; } @@ -448,7 +445,9 @@ def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, let AddedComplexity = 5; } def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, - ArithLogic16Defs<0>; + ArithLogic16Defs<0> { + let isCodeGenOnly = 1; +} def AddiuRxRyOffMemX16: FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; @@ -602,7 +601,7 @@ def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { let isBarrier=1; } -def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> { +def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> { let isBranch = 1; let isIndirectBranch = 1; let isTerminator=1; @@ -620,7 +619,9 @@ def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { // Purpose: Load Byte (Extended) // To load a byte from memory as a signed value. // -def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad; +def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ + let isCodeGenOnly = 1; +} // // Format: LBU ry, offset(rx) MIPS16e @@ -628,14 +629,18 @@ def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad; // To load a byte from memory as a unsigned value. // def LbuRxRyOffMemX16: - FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad; + FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { + let isCodeGenOnly = 1; +} // // Format: LH ry, offset(rx) MIPS16e // Purpose: Load Halfword signed (Extended) // To load a halfword from memory as a signed value. // -def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad; +def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ + let isCodeGenOnly = 1; +} // // Format: LHU ry, offset(rx) MIPS16e @@ -643,7 +648,9 @@ def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad; // To load a halfword from memory as an unsigned value. // def LhuRxRyOffMemX16: - FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad; + FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { + let isCodeGenOnly = 1; +} // // Format: LI rx, immediate MIPS16e @@ -657,7 +664,9 @@ def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; // Purpose: Load Word (Extended) // To load a word from memory as a signed value. // -def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad; +def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ + let isCodeGenOnly = 1; +} // Format: LW rx, offset(sp) MIPS16e // Purpose: Load Word (SP-Relative, Extended) -- cgit v1.2.3-70-g09d2