From eaf1c98a7c38444d41d1c6dc2074736eec7d452f Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Wed, 11 Aug 2010 23:10:46 +0000 Subject: Move the ARM SSAT and USAT optional shift amount operand out of the instruction opcode. This also fixes part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 99d9f01c04..57dc3471b9 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1466,9 +1466,7 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn, decodeRd(insn)))); unsigned Pos = slice(insn, 20, 16); - if (Opcode == ARM::SSATlsl || - Opcode == ARM::SSATasr || - Opcode == ARM::SSAT16) + if (Opcode == ARM::SSAT || Opcode == ARM::SSAT16) Pos += 1; MI.addOperand(MCOperand::CreateImm(Pos)); @@ -1476,12 +1474,17 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn, decodeRm(insn)))); if (NumOpsAdded == 4) { + ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl); // Inst{11-7} encodes the imm5 shift amount. unsigned ShAmt = slice(insn, 11, 7); - // A8.6.183. Possible ASR shift amount of 32... - if ((Opcode == ARM::SSATasr || Opcode == ARM::USATasr) && ShAmt == 0) - ShAmt = 32; - MI.addOperand(MCOperand::CreateImm(ShAmt)); + if (ShAmt == 0) { + // A8.6.183. Possible ASR shift amount of 32... + if (Opc == ARM_AM::asr) + ShAmt = 32; + else + Opc = ARM_AM::no_shift; + } + MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt))); } return true; } -- cgit v1.2.3-18-g5258