From ce1868b21ce91245622964da1408cdec76af77a8 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Thu, 24 Mar 2011 17:04:22 +0000 Subject: Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 2 ++ 1 file changed, 2 insertions(+) (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index cc2469f8c2..a9d41325de 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -2946,6 +2946,8 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, // of optional arguments is implemented. if (Opcode == ARM::CPS3p) { // Let's reject impossible imod values by returning false. + // AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an + // invalid combination, so we just check for imod=0b00 here. if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1) return false; MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod -- cgit v1.2.3-70-g09d2