From b45b11bce1fd79b0973d2df8db295583b5477c62 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Wed, 31 Aug 2011 22:00:41 +0000 Subject: The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index f4ca9ecc5d..0c2abe28ec 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2603,17 +2603,17 @@ DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, unsigned pred = fieldFromInstruction32(Insn, 22, 4); if (pred == 0xE || pred == 0xF) { - unsigned opc = fieldFromInstruction32(Insn, 4, 2); + unsigned opc = fieldFromInstruction32(Insn, 4, 28); switch (opc) { default: return Fail; - case 0: + case 0xf3bf8f4: Inst.setOpcode(ARM::t2DSB); break; - case 1: + case 0xf3bf8f5: Inst.setOpcode(ARM::t2DMB); break; - case 2: + case 0xf3bf8f6: Inst.setOpcode(ARM::t2ISB); return Success; } -- cgit v1.2.3-18-g5258