From b422d0b65e15435b6aef4a92f5663db9ec6659d4 Mon Sep 17 00:00:00 2001 From: Silviu Baranga Date: Thu, 3 May 2012 16:38:40 +0000 Subject: Fixed disassembler for vstm/vldm ARM VFP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 4c96c1acc9..28ea0d256e 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1224,8 +1224,8 @@ static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; - unsigned Vd = fieldFromInstruction32(Val, 8, 4); - unsigned regs = Val & 0xFF; + unsigned Vd = fieldFromInstruction32(Val, 8, 5); + unsigned regs = fieldFromInstruction32(Val, 0, 8); if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail; @@ -1241,8 +1241,10 @@ static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; - unsigned Vd = fieldFromInstruction32(Val, 8, 4); - unsigned regs = (Val & 0xFF) / 2; + unsigned Vd = fieldFromInstruction32(Val, 8, 5); + unsigned regs = fieldFromInstruction32(Val, 0, 8); + + regs = regs >> 1; if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail; -- cgit v1.2.3-18-g5258