From 399cdca4d201f7232126c3a0643669971ede780a Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Tue, 25 Oct 2011 00:14:01 +0000 Subject: ARM assembly parsing and encoding for VLD1 with writeback. Four entry register lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index ddc5c99d36..5174134c46 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2078,10 +2078,14 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD1d32Twb_register: case ARM::VLD1d64Twb_fixed: case ARM::VLD1d64Twb_register: - case ARM::VLD1d8Q_UPD: - case ARM::VLD1d16Q_UPD: - case ARM::VLD1d32Q_UPD: - case ARM::VLD1d64Q_UPD: + case ARM::VLD1d8Qwb_fixed: + case ARM::VLD1d8Qwb_register: + case ARM::VLD1d16Qwb_fixed: + case ARM::VLD1d16Qwb_register: + case ARM::VLD1d32Qwb_fixed: + case ARM::VLD1d32Qwb_register: + case ARM::VLD1d64Qwb_fixed: + case ARM::VLD1d64Qwb_register: case ARM::VLD2d8_UPD: case ARM::VLD2d16_UPD: case ARM::VLD2d32_UPD: -- cgit v1.2.3-18-g5258