From d5dc9eca2beece0faa85e7cbf17182fe7fcd0b36 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Fri, 1 Jul 2011 00:30:46 +0000 Subject: Add support for the ARM 't' register constraint. And another testcase for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'lib/Target/ARM/ARMISelLowering.cpp') diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 1141f42f14..4a78ad4bf2 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -7484,6 +7484,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const { case 'w': return C_RegisterClass; case 'h': return C_RegisterClass; case 'x': return C_RegisterClass; + case 't': return C_RegisterClass; } } else if (Constraint.size() == 2) { switch (Constraint[0]) { @@ -7563,6 +7564,10 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, if (VT.getSizeInBits() == 128) return RCPair(0U, ARM::QPR_8RegisterClass); break; + case 't': + if (VT == MVT::f32) + return RCPair(0U, ARM::SPRRegisterClass); + break; } } if (StringRef("{cc}").equals_lower(Constraint)) -- cgit v1.2.3-70-g09d2