From bd17bc96bf54cc58d91c2d20964c6c5e28bffa57 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 25 Mar 2010 23:32:19 +0000 Subject: switch the flag for using NEON for SP floating point to a subtarget 'feature' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARM.td | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'lib/Target/ARM/ARM.td') diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 50d54b436e..931c81c5b6 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -49,8 +49,14 @@ def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", // FIXME: Currently, this is only flagged for Cortex-A8. It may be true for // others as well. We should do more benchmarking and confirm one way or // the other. -def HasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true", - "Disable VFP MAC instructions">; +def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true", + "Disable VFP MAC instructions">; +// Some processors benefit from using NEON instructions for scalar +// single-precision FP operations. +def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", + "true", + "Use NEON for single precision FP">; + //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -115,7 +121,8 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries, // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, - [ArchV7A, FeatureThumb2, FeatureNEON, HasSlowVMLx]>; + [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx, + FeatureNEONForFP]>; def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; //===----------------------------------------------------------------------===// -- cgit v1.2.3-18-g5258