From 3d45a853db014fdddcdb79424e663dfed5eccbc7 Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Thu, 3 Sep 2009 22:53:57 +0000
Subject: LLVM currently represents floating-point negation as -0.0 - x. Fix
 FastISel to recognize this pattern and emit a floating-point negation using
 xor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80963 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/FastISel.cpp | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'lib/CodeGen/SelectionDAG/FastISel.cpp')

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 5b4c79a9fd..f0c7086184 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -608,6 +608,26 @@ FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
   MBB->addSuccessor(MSucc);
 }
 
+/// SelectFNeg - Emit an FNeg operation.
+///
+bool
+FastISel::SelectFNeg(User *I) {
+  unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
+  if (OpReg == 0) return false;
+
+  // Twiddle the sign bit with xor.
+  EVT VT = TLI.getValueType(I->getType());
+  if (VT.getSizeInBits() > 64) return false;
+  unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISD::XOR, OpReg,
+                                    UINT64_C(1) << (VT.getSizeInBits()-1),
+                                    VT.getSimpleVT());
+  if (ResultReg == 0)
+    return false;
+
+  UpdateValueMap(I, ResultReg);
+  return true;
+}
+
 bool
 FastISel::SelectOperator(User *I, unsigned Opcode) {
   switch (Opcode) {
@@ -618,6 +638,9 @@ FastISel::SelectOperator(User *I, unsigned Opcode) {
   case Instruction::Sub:
     return SelectBinaryOp(I, ISD::SUB);
   case Instruction::FSub:
+    // FNeg is currently represented in LLVM IR as a special case of FSub.
+    if (BinaryOperator::isFNeg(I))
+      return SelectFNeg(I);
     return SelectBinaryOp(I, ISD::FSUB);
   case Instruction::Mul:
     return SelectBinaryOp(I, ISD::MUL);
-- 
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