From 73ba69b6843f7f23345b1e8745cb328952cae0d8 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Wed, 7 Mar 2012 05:21:40 +0000 Subject: misched preparation: modularize schedule printing. ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/ScheduleDAG.cpp | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'lib/CodeGen/ScheduleDAG.cpp') diff --git a/lib/CodeGen/ScheduleDAG.cpp b/lib/CodeGen/ScheduleDAG.cpp index de8f5199eb..7fae783f8d 100644 --- a/lib/CodeGen/ScheduleDAG.cpp +++ b/lib/CodeGen/ScheduleDAG.cpp @@ -52,17 +52,6 @@ const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const { return &TII->get(Node->getMachineOpcode()); } -/// dump - dump the schedule. -void ScheduleDAG::dumpSchedule() const { - for (unsigned i = 0, e = Sequence.size(); i != e; i++) { - if (SUnit *SU = Sequence[i]) - SU->dump(this); - else - dbgs() << "**** NOOP ****\n"; - } -} - - /// Run - perform scheduling. /// void ScheduleDAG::Run(MachineBasicBlock *bb, @@ -76,12 +65,6 @@ void ScheduleDAG::Run(MachineBasicBlock *bb, ExitSU = SUnit(); Schedule(); - - DEBUG({ - dbgs() << "*** Final schedule ***\n"; - dumpSchedule(); - dbgs() << '\n'; - }); } /// addPred - This adds the specified edge as a pred of the current node if -- cgit v1.2.3-70-g09d2