From bf9716b9c48d3b0370c715cd79540945f73dc296 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 30 Sep 2005 01:29:00 +0000 Subject: Change this code ot pass register classes into the stack slot spiller/reloader code. PrologEpilogInserter hasn't been updated yet though, so targets cannot use this info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23536 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocSimple.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib/CodeGen/RegAllocSimple.cpp') diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index b27f1b7079..57f3f5d772 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -135,7 +135,7 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, // Add move instruction(s) ++NumLoads; - RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx); + RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); return PhysReg; } @@ -147,7 +147,7 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, // Add move instruction(s) ++NumStores; - RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx); + RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC); } -- cgit v1.2.3-70-g09d2