From 73e7dced3892f2abb4344526147d4df0f62aee61 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 29 Jul 2011 22:51:22 +0000 Subject: Add an isSSA() flag to MachineRegisterInfo. This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136532 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineRegisterInfo.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/CodeGen/MachineRegisterInfo.cpp') diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp index 4b3e64c25f..62dd576878 100644 --- a/lib/CodeGen/MachineRegisterInfo.cpp +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -17,7 +17,8 @@ #include "llvm/Support/CommandLine.h" using namespace llvm; -MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { +MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) + : IsSSA(true) { VRegInfo.reserve(256); RegAllocHints.reserve(256); UsedPhysRegs.resize(TRI.getNumRegs()); -- cgit v1.2.3-70-g09d2