From 913d3dfac43f29921467f33aa743f28ee1bfc5d1 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Fri, 12 Sep 2008 17:49:03 +0000 Subject: Pass "earlyclobber" bit through to machine representation; coalescer and RA need to know about it. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56161 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineInstr.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'lib/CodeGen/MachineInstr.cpp') diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 9fbae68479..4cdf064245 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -104,7 +104,8 @@ void MachineOperand::ChangeToImmediate(int64_t ImmVal) { /// the specified value. If an operand is known to be an register already, /// the setReg method should be used. void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, - bool isKill, bool isDead) { + bool isKill, bool isDead, + bool isEarlyClobber) { // If this operand is already a register operand, use setReg to update the // register's use/def lists. if (isReg()) { @@ -126,6 +127,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, IsImp = isImp; IsKill = isKill; IsDead = isDead; + IsEarlyClobber = isEarlyClobber; SubReg = 0; } @@ -181,13 +183,15 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { OS << "%mreg" << getReg(); } - if (isDef() || isKill() || isDead() || isImplicit()) { + if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) { OS << "<"; bool NeedComma = false; if (isImplicit()) { OS << (isDef() ? "imp-def" : "imp-use"); NeedComma = true; } else if (isDef()) { + if (isEarlyClobber()) + OS << "earlyclobber,"; OS << "def"; NeedComma = true; } -- cgit v1.2.3-18-g5258