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2011-10-10Emit full ED initializers even for pseudo-instructions.Jakob Stoklund Olesen
This should unbreak the picky buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen
The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Remove MultidefsDavid Greene
Multidefs are a bit unwieldy and incomplete. Remove them in favor of another mechanism, probably for loops. Revert "Make Test More Thorough" Revert "Fix a typo." Revert "Vim Support for Multidefs" Revert "Emacs Support for Multidefs" Revert "Document Multidefs" Revert "Add a Multidef Test" Revert "Update Test for Multidefs" Revert "Process Multidefs" Revert "Parser Multidef Support" Revert "Lexer Support for Multidefs" Revert "Add Multidef Data Structures" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper
64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Remove the Clang tblgen backends from LLVM.Peter Collingbourne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper
was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Build system infrastructure for multiple tblgens.Peter Collingbourne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Remove the TRI::getSubRegisterRegClass() hook.Jakob Stoklund Olesen
This restores my karma after I added TRI::getSubClassWithSubReg(). Register constraints are applied 'backwards'. Starting from the register class required by an instruction operand, the correct question is: 'How can I constrain the super-register register class so all its sub-registers satisfy the instruction constraint?' The getMatchingSuperRegClass() hook answers that. We never need to go 'forwards': Starting from a super-register register class, what register class are the sub-registers in? The getSubRegisterRegClass() hook did that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Vim Support for MultidefsDavid Greene
Add vim highlighting support for multidefs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Emacs Support for MultidefsDavid Greene
Add Emacs font-lock keyword support for multidefs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen
This function is used to constrain a register class to a sub-class that supports the given sub-register index. For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD. The function will be used to compute register classes when emitting INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation of sub-register operations. The version provided by TableGen is usually adequate, but targets can override. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Properly use const_iterator.Jakob Stoklund Olesen
This should unbreak the Windows build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Teach TableGen to infer missing register classes.Jakob Stoklund Olesen
The set of register classes should be closed under sub-register operations and intersections. That will allow the register allocator to model combinations of constraints accurately. This patch implements the easiest form of register class inference: For every register class, and for every sub-register SubIdx, the subset of registers in RC that have a SubIdx sub-register should also be a register class. This does create some new register classes for the targets in the tree: ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td file on purpose because it only has two registers. InstrEmitter and RegisterCoalescer have safeguards against selecting too small register classes, so it is harmless. PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32 sub-register of LR8. I think that might be an omission? X86 puts RIP in the GR64 class, and since that register doesn't have 8-bit sub-registers, we get: GR64_with_sub_8bit GR64_TC_with_sub_8bit GR64_NOREX_with_sub_8bit GR64_TC_with_sub_8bit_hi The various CodeGen classes have already been fixed so adding new register classes should not affect compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Store all allocation orders together.Jakob Stoklund Olesen
There is no need to keep the primary order separate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen
When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Don't add synthetic Records to the RecordKeeper.Jakob Stoklund Olesen
The RecordKeeper could be shared by multiple target instances, causing duplicate record errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper
instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Remove last references to hotpatch.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Find the strip tool that works with the specified SDKROOT. rdar://10165908Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-02Fix typo in r140954.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper
0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne
This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Subtarget getFeatureBits() returns a uint64_t, not unsigned.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140928 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().Jakob Stoklund Olesen
All the sub-class bit vectors are computed when first creating the register bank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Store sub-class lists as a bit vector.Jakob Stoklund Olesen
This uses less memory and it reduces the complexity of sub-class operations: - hasSubClassEq() and friends become O(1) instead of O(N). - getCommonSubClass() becomes O(N) instead of O(N^2). In the future, TableGen will infer register classes. This makes it cheap to add them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Extract a slightly more general BitVector printer.Jakob Stoklund Olesen
This one can also print 32-bit groups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Compute lists of super-classes in CodeGenRegisterClass.Jakob Stoklund Olesen
Use these lists instead of computing them on the fly in RegisterInfoEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Implement VarListElementInit:: resolveListElementReferenceDavid Greene
Implement VarListElementInit:: resolveListElementReference so that lists of lists can be indexed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Precompute a bit vector of register sub-classes.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140827 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Order register classes topologically.Jakob Stoklund Olesen
All register classes are given a lower ID than their sub-classes. Cliques are ordered alphabetically. This will be used to simplify some sub-class operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen
This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29tblgen/ClangDiagnostics: Add support for split default warning "no-werror" andDaniel Dunbar
"show-in-system-header" bits, which I will be adding in Clang shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26Remove old hack for compiling with gcc-4.0.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140573 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-25Add target hook for pseudo instruction expansion.Jakob Stoklund Olesen
Many targets use pseudo instructions to help register allocation. Like the COPY instruction, these pseudos can be expanded after register allocation. The early expansion can make life easier for PEI and the post-ra scheduler. This patch adds a hook that is called for all remaining pseudo instructions from the ExpandPostRAPseudos pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper
Fixes part of PR10700. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20Restore hasPostISelHook tblgen flag.Andrew Trick
No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20ARM isel bug fix for adds/subs operands.Andrew Trick
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20Remove more of llvmc and dependencies.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Better Error ReportingDavid Greene
Report missing template arguments more helpfully by supplying the name of the missing argument in the error message. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Migrate this to use clang by default as well.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16We now look for clang, then llvm-gcc, then gcc as our compiler. We don't needEric Christopher
this anymore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND ↵Craig Topper
from being recognized by disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13[tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to ↵Argyrios Kyrtzidis
attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139617 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13In ClangAttrEmitter.cpp emit code that allows attributes to keep their ↵Argyrios Kyrtzidis
source range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139598 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from ↵Craig Topper
being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-11Fix disassembling of reverse register/register forms of ↵Craig Topper
ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-23 09:22:29 +0000