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2012-07-23Fix a typo (the the => the)Sylvestre Ledru
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-20lit: Use close_fds=True on UNIX, to avoid file descriptor pollution ofDaniel Dunbar
subprocesses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Move around some enum elements so that lastMRM corrects gets assigned 56, whichRichard Trieu
is one more that MRM_DF which is 55. Previously, it held value 45, the same as MRM_D0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18TblGen: Tweak to pretty-print DAGISel.inc a bit better.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper
instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17TableGen: Pattern<> references to null_frag are a nop.Jim Grosbach
A standalone pattern defined in a multiclass expansion should handle null_frag references just like patterns on instructions. Follow-up to r160333. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160384 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17TableGen: Allow conditional instruction pattern in multiclass.Jim Grosbach
Define a 'null_frag' SDPatternOperator node, which if referenced in an instruction Pattern, results in the pattern being collapsed to be as-if '[]' had been specified instead. This allows supporting a multiclass definition where some instaniations have ISel patterns associated and others do not. For example, multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> { def _x : myI<(outs rc:), (ins rc:), []>; def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>; } defm foo : myMulti<GRa, not>; defm bar : myMulti<GRb>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Defer checking for registers in the MC AsmMatcher until the after ↵Owen Anderson
user-defined match classes have been checked. This allows the creation of MatchClass's that are supersets of a register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12TableGen: Assembly matcher 'insufficient operands' diagnostic.Jim Grosbach
Make sure the tblgen'erated asm matcher correctly returns numoperands+1 as the ErrorInfo when the problem was that there weren't enough operands specified. rdar://9142751 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160144 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper
myself and Manman Ren. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Machine model: allow itineraries to be shared by different processor models.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07Tweak spelling.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159889 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Revert r159528 which taught lit's builtin shell test runner about theChandler Carruth
'|&' bash syntax. We have lots of users with a bash on their system which doesn't support this syntax, and as bash is still significantly faster, we should support them. The test suite has already been updated to cope with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Fix the C++11 build. I hate narrowing conversions.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Teach the built-in shell test runner in lit to handle '|&'-style pipes.Chandler Carruth
This is directly cloned from the logic in the TCL test bits of lit. Hopefully will fix most of the windows build bot fallout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick
The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Fix Windows build after r159281: s/iterator/const_iteratorAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Silence unused variable warning.Richard Trieu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Refactor and speed up DFA generator.Anshuman Dasgupta
Patch by Ivan Llopard! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26TableGen: AsmMatcher diagnostics preference detail.Jim Grosbach
Don't override a custom diagnostic w/ a generic InvalidOperand, all else being equal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159238 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26X86: add GATHER intrinsics (AVX2) in LLVMManman Ren
Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Teach TableGen to put chains on more instructionsTim Northover
When generating selection tables for Pat instances, TableGen relied on an output Instruction's Pattern field being set to infer whether a chain should be added. This patch adds additional logic to check various flag fields so that correct code can be generated even if Pattern is unset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159217 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Typo.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22TableGen: AsmMatcher support for better operand diagnostics.Jim Grosbach
"Invalid operand" may be a completely correct diagnostic, but it's often insufficiently specific to really help identify and fix the problem in assembly source. Allow a target to specify a more-specific diagnostic kind for each AsmOperandClass derived definition and use that to provide more detailed diagnostics when an operant of that class resulted in a match failure. rdar://8987109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Revert r158679 - use case is unclear (and it increases the memory footprint).Hal Finkel
Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Reverting makefile change wile I figure out what the heck happenedMarshall Clow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159017 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Added building yaml2obj to the configure+make build systemMarshall Clow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Use "NoItineraries" for processors with no itineraries.Andrew Trick
This makes it explicit when ScoreboardHazardRecognizer will be used. "GenericItineraries" would only make sense if it contained real itinerary values and still required ScoreboardHazardRecognizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19New test tool: obj2yamlMarshall Clow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18Allow up to 64 functional units per processor itinerary.Hal Finkel
This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158679 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18TableGen: AsmMatcher missing-features list minimization.Jim Grosbach
When returning a 'cannot match due to missing CPU features' error code, if there are multiple potential matches with different feature sets, return the smallest set of missing features from the alternatives as that's most likely to be the one that's desired. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12Add two newlines in ParseSubtargetFeatures's debug output after the CPU is ↵Hal Finkel
printed. There is otherwise not a newline between the CPU name and the start of the next pass's output which makes both difficult to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158350 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen
The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Sched itinerary fix: Avoid static initializers.Andrew Trick
This fixes an accidental dependence on static initialization order that I introduced yesterday. Thank you Lang!!! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158215 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a ↵Owen Anderson
complex operand are called out explicitly in the asm string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove dead private member variables from gtest.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Round 2 of dead private variable removal.Benjamin Kramer
LLVM is now -Wunused-private-field clean except for - lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields. - gtest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Fix gtest build issue on Visual Studio 2012 RCJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: Added MultiIssueItineraries.Andrew Trick
This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-02Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Didn't mean to export this function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Emit register unit root tables.Jakob Stoklund Olesen
Each register unit has one or two root registers. The full set of registers containing a given register unit can be computed as the union of the root registers and their super-registers. Provide an MCRegUnitRootIterator class to enumerate the roots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Print uint16_t numbers without a sign.Jakob Stoklund Olesen
It seems I broke C++11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Remove little semicolon that caused a lot of warnings.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29Emit register unit lists for each register.Jakob Stoklund Olesen
Register units are already used internally in TableGen to compute register pressure sets and overlapping registers. This patch makes them available to the code generators. The register unit lists are differentially encoded so they can be reused for many related registers. This keeps the total size of the lists below 200 bytes for most targets. ARM has the largest table at 560 bytes. Add an MCRegUnitIterator for traversing the register unit lists. It provides an abstract interface so the representation can be changed in the future without changing all clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
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