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2011-06-29ARM RSCS* don't need explicit TableGen decoder checks.Jim Grosbach
They've been pseudos for a while now, so the decoder will never see them in the first place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach
The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Change AsmName's type from StringRef to std::string. AsmName was pointing to ↵Francois Pichet
a temporary string object that was destroyed. This is undefined behavior and MSVC didn't like it. This fixes over 300+ failing tests on MSVC. Credit for this fix goes to chapuni. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng
MCInstrItineraries) into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Add MCInstrInfo registeration machinery.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Alternative name enum should go into the enum portion.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27ARM Assembly support for Thumb mov-immediate.Jim Grosbach
Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Remove RCBarriers from TargetInstrDesc.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Add support for alternative register names, useful for instructions whose ↵Owen Anderson
operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27More refactoring. MC doesn't need know about subreg indices.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng
into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25Remove dead typedefs.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Rename TargetRegisterDesc to MCRegisterDescEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix."Bob Wilson
Sorry, this was a bad idea. Within clang these builtins are in a separate "ARM" namespace, but the actual builtin names should clearly distinguish that they are target specific. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Shorten some ARM builtin names by removing unnecessary "neon" prefix.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24- Add MCRegisterInfo registration machinery. Also added x86 registration ↵Evan Cheng
routines. - Rename TargetRegisterDesc to MCRegisterDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Make the generated InitXXXMCRegisterInfo function "static inline", so it ↵Benjamin Kramer
doesn't get emitted into multiple object files. This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen into a single binary (for example when building a monolithic libLLVM shared library). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22lit support for REQUIRES: asserts.Andrew Trick
Take #2. Don't piggyback on the existing config.build_mode. Instead, define a new lit feature for each build feature we need (currently just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define this feature within test/lit.site.cfg. This doesn't require any lit harness changes and should be more robust across build systems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Unbreak the CMake buildFrancois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133574 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Consolidate some TableGen diagnostic helper functions.Jim Grosbach
TableGen had diagnostic printers sprinkled about in a few places. Pull them together into a single location in Error.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Skip fields that don't exist in the Register class.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Add a RegisterTuples class to Target.td and TableGen.Jakob Stoklund Olesen
A RegisterTuples instance is used to synthesize super-registers by zipping together lists of sub-registers. This is useful for generating pseudo-registers representing register sequence constraints like 'two consecutive GPRs', or 'an even-odd pair of floating point registers'. The RegisterTuples def can be used in register set operations when building register classes. That is the only way of accessing the synthesized super-registers. For example, the ARM QQ register class of pseudo-registers could have been formed like this: // Form pairs Q0_Q1, Q2_Q3, ... def QQPairs : RegisterTuples<[qsub_0, qsub_1], [(decimate QPR, 2), (decimate (shl QPR, 1), 2)]>; def QQ : RegisterClass<..., (add QQPairs)>; Similarly, pseudo-registers representing '3 consecutive D-regs with wraparound' look like: // Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1. def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2], [(rotl DPR, 0), (rotl DPR, 1), (rotl DPR, 2)]>; TableGen automatically computes aliasing information for the synthesized registers. Register tuples are still somewhat experimental. We still need to see how they interact with MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18fix the varargs version of StructType::get to not require an LLVMContext, ↵Chris Lattner
making usage much cleaner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133364 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Use the correct comparator to avoid depending on pointer values.Jakob Stoklund Olesen
This should fix the Linux buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133334 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen
Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Remove MethodProtos/MethodBodies and allocation_order_begin/end.Jakob Stoklund Olesen
Targets that need to change the default allocation order should use the AltOrders mechanism instead. See the X86 and ARM targets for examples. The allocation_order_begin() and allocation_order_end() methods have been replaced with getRawAllocationOrder(), and there is further support functions in RegisterClassInfo. It is no longer possible to insert arbitrary code into generated register classes. This is a feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Provide AltOrders for specifying alternative allocation orders.Jakob Stoklund Olesen
A register class can define AltOrders and AltOrderSelect instead of defining method protos and bodies. The AltOrders lists can be defined with set operations, and TableGen can verify that the alternative allocation orders only contain valid registers. This is currently an opt-in feature, and it is still possible to override allocation_order_begin/end. That will not be true for long. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Fix formatting.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Prempt some obnoxious compiler from complaing about signed/unsignedJakob Stoklund Olesen
compares. 2^30 is actually the limit on the number of physical registers per TargetRegisterInfo.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Make sure to pass an unsigned to a printf format that is always %u.Jakob Stoklund Olesen
This should unbreak the native ARM testers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Add support to lit for build mode requirements. e.g.Andrew Trick
REQUIRES: Asserts REQUIRES: Debug This required chaining test configuration properties. It seems like a generally good thing to do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson
features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Update the Clang diagnostic emitter to emit IDs for diagnostic categories.John McCall
Patch by Argyrios Kyrtzidis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Add a new function attribute, nonlazybind, which inhibits lazy-loadingJohn McCall
optimizations when emitting calls to the function; instead those calls may use faster relocations which require the function to be immediately resolved upon loading the dynamic object featuring the call. This is useful when it is known that the function will be called frequently and pervasively and therefore there is no merit in delaying binding of the function. Currently only implemented for x86-64, where it turns into a call through the global offset table. Patch by Dan Gohman, who assures me that he's going to add LangRef documentation for this once it's committed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Replace the statically generated hashtables for checking register ↵Owen Anderson
relationships with just scanning the (typically tiny) static lists. At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries. Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan. With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time. It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133051 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Use a SetTheory instance to expand register lists in register classes.Jakob Stoklund Olesen
This prepares tablegen to compute register lists from set theoretic dag expressions. This doesn't really make any difference as long as Target.td still declares RegisterClass::MemberList as [Register]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen
Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Improve the heuristic to emit the alias if the number of hard-coded registersBill Wendling
are also greater than the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen
No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14Fix a compile time regression caused by too small hash tables.Jakob Stoklund Olesen
Measure the worst case number of probes for a miss instead of the less conservative number of probes required for an insertion. Lower the limit to < 6 probes worst case. This doubles the size of the ARM and X86 hash tables, other targets are unaffected. LiveVariables runs 12% faster with this change. <rdar://problem/9598545> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132999 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14Heuristic: If the number of operands in the alias are more than the number ofBill Wendling
operands in the aliasee, don't print the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Tweak hash function and compress hash tables.Jakob Stoklund Olesen
Make the hash tables as small as possible while ensuring that all lookups can be done in less than 8 probes. Cut the aliases hash table in half by only storing a < b pairs - it is a symmetric relation. Use larger multipliers on the initial hash function to ensure that it properly covers the whole table, and to resolve some clustering in the very regular ARM register bank. This reduces the size of most of these tables by 4x - 8x. For instance, the ARM tables shrink from 48 KB to 8 KB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Remove now dead code.Jakob Stoklund Olesen
These computations have been moved to CodeGenRegisters.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Extract the generateHashTable function.Jakob Stoklund Olesen
The constant hash tables for sub-registers and overlaps are generated the same way, so extract a function to generate and print the hash table. Also use the information computed by CodeGenRegisters.cpp instead of the locally data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Compute lists of sub-regs, super-regs, and overlapping regs.Jakob Stoklund Olesen
Besides moving structural computations to CodeGenRegisters.cpp, this also well-defines the order of these lists: - Sub-register lists come from a pre-order traversal of the graph defined by the SubRegs lists in the .td files. - Super-register lists are topologically ordered so no register comes before any of its sub-registers. When the sub-register graph is not a tree, independent super-registers appear in numerical order. - Lists of overlapping registers are ordered according to register number. This reverses the order of the super-regs lists, but nobody was depending on that. The previous order of the overlaps lists was odd, and it may have depended on the precise behavior of std::stable_sort. The old computations are still there, but will be removed shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-24 11:56:32 +0000