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2011-04-15Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some ↵Evan Cheng
targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Fix a ton of comment typos found by codespell. Patch byChris Lattner
Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13Add an option to not print the alias of an instruction. It defaults to "printBill Wendling
the alias". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen
rdar://problem/9267838 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11TableGen: Keep the order of DECL_CONTEXT() for DeclNodes.td. RecordVector ↵NAKAMURA Takumi
may be used instead of RecordSet. The result of DeclNodes.inc was unstable on msys, Windows 7 x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08Only emit the AvailableFeatures variable if it's used.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Replace the old algorithm that emitted the "print the alias for an instruction"Bill Wendling
with the newer, cleaner model. It uses the IAPrinter class to hold the information that is needed to match an instruction with its alias. This also takes into account the available features of the platform. There is one bit of ugliness. The way the logic determines if a pattern is unique is O(N**2), which is gross. But in reality, the number of items it's checking against isn't large. So while it's N**2, it shouldn't be a massive time sink. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Add support for the VIA PadLock instructions.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Use array_lengthofJoerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04Change loops to derive the number of tables automaticallyJoerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01tlbgen/MC: StringRef's to temporary objects considered harmful.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Add annotations to tablegen-generated processor itineraries, or replace them ↵Andrew Trick
with something meaningful. I want to be able to read and debug the generated tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31Use intrinsics for Neon vmull operations. Radar 9208957.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30ClangSAEmClangSACheckersEmitter, emit info about groups.Argyrios Kyrtzidis
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29Quiet a gcc warning about changed name lookup rulesMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29In ClangSACheckersEmitter:Argyrios Kyrtzidis
- Also emit a list of packages and groups sorted by name - Avoid iterating over DenseSet so that the output of the arrays is deterministic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29For ClangSACheckersEmitter, allow a package to belong to checker group, in ↵Argyrios Kyrtzidis
which all its checkers will go into the group. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26Extend Clang's TableGen emitter for attributes to support bool arguments.Douglas Gregor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen
instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen
stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen
was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23Update the Clang attribute emitter to handle attributes of 'version'Douglas Gregor
kind, and fix serialization/deserialization of IdentifierInfo attributes. These are requires for the new 'availability' attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21Call static functions so that they aren't left unused.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128020 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21A WIP commit of the InstAlias printing cleanup. This code will soon replace theBill Wendling
code below it. Even though it looks very similar, it will match more precisely and geneate better functions in the long run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127991 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21Add the IAPrinter class.Bill Wendling
This is a helper class that will make it easier to say which InstAliases can be printed and which cannot (because of ambiguity). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21* Add classes that support the "feature" information.Bill Wendling
* Move the code that emits the reg in reg class matching into its own function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127988 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15- Add "Bitcast" target instruction property for instructions which performEvan Cheng
nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15X86 table-generator and disassembler support for the AVXSean Callanan
instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14Ignore isCodeGenOnly instructions when generating diassembly tables.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14Correct small comment order typo.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12Remove no-longer-correct special case for disasm of ARM BL instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Pseudo-ize the ARM 'B' instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127491 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach
as for VDUP32d and VDUP32q, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach
and VDUPLN32d, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach
as for VREV64d32 and VREV64q32, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Add missing 'return on failure'. Previously we'd crash after emittingJim Grosbach
the diagnostic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127480 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Teach TableGen to pre-calculate register enum values when creating theJim Grosbach
CodeGenRegister entries. Use this information to more intelligently build the literal register entires in the DAGISel matcher table. Specifically, use a single-byte OPC_EmitRegister entry for registers with a value of less than 256 and OPC_EmitRegister2 entry for registers with a larger value. rdar://9066491 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Make the register enum value part of the CodeGenRegister struct.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127446 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-22 18:19:28 +0000