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2011-06-12Tweak hash function and compress hash tables.Jakob Stoklund Olesen
Make the hash tables as small as possible while ensuring that all lookups can be done in less than 8 probes. Cut the aliases hash table in half by only storing a < b pairs - it is a symmetric relation. Use larger multipliers on the initial hash function to ensure that it properly covers the whole table, and to resolve some clustering in the very regular ARM register bank. This reduces the size of most of these tables by 4x - 8x. For instance, the ARM tables shrink from 48 KB to 8 KB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Remove now dead code.Jakob Stoklund Olesen
These computations have been moved to CodeGenRegisters.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Extract the generateHashTable function.Jakob Stoklund Olesen
The constant hash tables for sub-registers and overlaps are generated the same way, so extract a function to generate and print the hash table. Also use the information computed by CodeGenRegisters.cpp instead of the locally data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Compute lists of sub-regs, super-regs, and overlapping regs.Jakob Stoklund Olesen
Besides moving structural computations to CodeGenRegisters.cpp, this also well-defines the order of these lists: - Sub-register lists come from a pre-order traversal of the graph defined by the SubRegs lists in the .td files. - Super-register lists are topologically ordered so no register comes before any of its sub-registers. When the sub-register graph is not a tree, independent super-registers appear in numerical order. - Lists of overlapping registers are ordered according to register number. This reverses the order of the super-regs lists, but nobody was depending on that. The previous order of the overlaps lists was odd, and it may have depended on the precise behavior of std::stable_sort. The old computations are still there, but will be removed shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen
Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen
Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Move TableGen's register bank classes to their own source file.Jakob Stoklund Olesen
I'll be moving some more code there to gather all of the register-specific stuff in one place. Currently it is shared between CodeGenTarget and RegisterInfoEmitter. The plan is that CodeGenRegisters can compute the full register bank structure while RegisterInfoEmitter only will handle the printing part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Add special-case range checking for VCVT_N intrinsic immediate operands.Bob Wilson
Radar 9558930. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132732 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04Drop a RecordKeeper reference that wasn't necessary.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04Silence compiler warnings.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04Teach TableGen to evaluate DAG expressions as set operations.Jakob Stoklund Olesen
A TableGen backend can define how certain classes can be expanded into ordered sets of defs, typically by evaluating a specific field in the record. The SetTheory class can then evaluate DAG expressions that refer to these named sets. A number of standard set and list operations are predefined, and the backend can add more specialized operators if needed. The -print-sets backend is used by SetTheory.td to provide examples. This is intended to simplify how register classes are defined: def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Make it possible to have unallocatable register classes.Jakob Stoklund Olesen
Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Add new -d option to tblgen. It writes a make(1)-style dependency file.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes
must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola
directives. Fixes PR9826. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30Introduce the DwarfRegAlias class for declaring that two registers have theRafael Espindola
same dwarf number. This will be used for creating a dwarf number to register mapping. The only case that needs this so far is the XMM/YMM registers that unfortunately do have the same numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Change how tblgen generates attributes for intrinsics to use a singleJohn McCall
switch. With this newfound organization, teach tblgen how not to give all intrinsics the 'nounwind' attribute. Introduce a new intrinsic, llvm.eh.resume, which does not have this attribute. Documentation and uses to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Fix the root cause of the bootstrap failure:Rafael Espindola
There was no way to check if a given register/mode pair was valid. We now return an error code (-2) instead of asserting. If anyone thinks that an assert at this point is really needed, we can autogen a hasValidDwarfRegNum instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25[tablegen] A couple of changes to ClangDiagnosticEmmitter.Argyrios Kyrtzidis
-Emit an empty warning option as string ("") instead of 0. -For diagnostic names also emit the size of the string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23Use a more efficient data structure for the "operand map". The number ofBill Wendling
operands to an instruction aren't great, so an iterative search is fairly quick and doesn't have the overhead of std::map. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather thanCameron Zwarich
the root if there is only one such node. This leaves only 2 verifier failures in the entire test suite when running "make check". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10Downgrade a tablegen warning to an error.Jakob Stoklund Olesen
Ambiguous sub-register index compositions are OK as long as the backend writer knows what he is doing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09Fixed MC encoding for index_align for VLD1/VST1 (single element from one ↵Mon P Wang
lane) for size 32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07Teach TableGen to automatically generate missing SubRegIndex instances.Jakob Stoklund Olesen
The RegisterInfo.td file should only specify the indexes that sources need to refer to. The rest is inferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06Improve diagnostics for some parse errors. Not asserting when a user inputJim Grosbach
error is detected is a good thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06ParseFile() may throw, so extend the try/catch to handle that.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05llvmc: Make it possible to provide an argument to (join).Mikhail Glushenkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03Tidy up. Add missing newline to generated file.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29Filter out pattterns from the FastISel emitter which it doesn't actually ↵Eli Friedman
know how to handle. No significant functionality change at the moment, but it's necessary for some changes I'm planning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Fix a bug in tblgen that caused incorrect encodings on instructions that ↵Owen Anderson
specified operands with "bit" instead of "bits<1>". Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question. <rdar://problem/9345702> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130410 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-24Add a TODO.Mikhail Glushenkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23Remove unused STL header includes.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen
should print out ldr, not ldr.n. rdar://problem/9267772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22Define Neon load/store intrinsics for Clang as macros instead of functions.Bob Wilson
This is needed so the front-end can see "aligned" attributes on the type for the pointer arguments. Radar 9311427. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Don't allow per-register spill size and alignment.Jakob Stoklund Olesen
These values were not used for anything. Spill size and alignment is a property of the register class, not the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen
On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Invert the meaning of printAliasInstr's return value. It now returnsEric Christopher
true on success and false on failure. Update callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Enhance the fixed-length disassembler to support the callbacks necessary for ↵Owen Anderson
symbolic disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Add a new bit that ImmLeaf's can opt into, which allows them to duck out ofChris Lattner
the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Implement major new fastisel functionality: the matcher can now handle ↵Chris Lattner
immediates with value constraints on them (when defined as ImmLeaf's). This is particularly important for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand, which has a value constraint. Before this patch we ended up iseling the examples into such amazing code as: movabsq $7, %rax imulq %rax, %rdi movq %rdi, %rax ret now we produce: imulq $7, %rdi, %rax ret This dramatically shrinks the generated code at -O0 on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17introduce a new OpKind abstraction which wraps up operand flavors in a tidy ↵Chris Lattner
little wrapper. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17change OperandsSignature to use SmallVector<char> instead of std::vector<string>Chris Lattner
since the strings are always exactly one character, and there are usually only 2-3 operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17since the VT is fixed for a ImmLeaf, there is no reason to expose it to the ↵Chris Lattner
matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17now that predicates have a decent abstraction layer on them, introduce a new Chris Lattner
kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17Rework our internal representation of node predicates to expose moreChris Lattner
structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17remove some debugging code I added.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-171. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner
2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129666 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Initial work to improve documentation for Clang's diagnostics, from Matthieu ↵Douglas Gregor
Monrocq git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129613 91177308-0d34-0410-b5e6-96231b3b80d8
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