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2012-03-03Perform the string table optimization for OperandMatchEntries too.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151986 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-03Shrink the asm matcher tables.Benjamin Kramer
- Shrink the opcode field to 16 bits. - Shrink the AsmVariantID field to 8 bits. - Store the mnemonic string in a string table, store a 16 bit index. - Store a pascal-style length byte in the string instead of a null terminator, so we can avoid calling strlen on every entry we visit during mnemonic search. Shrinks X86AsmParser.o from 434k to 201k on x86_64 and eliminates relocs from the table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-03StringToOffsetTable: Allow uniquing the first element, add an option to skip ↵Benjamin Kramer
appending a terminating null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.Jim Grosbach
Allows us to de-virtualize the function and provides access to it in the instruction printer, which is useful for handling composite physical registers (e.g., ARM register lists). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach
This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer
function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Emit the "is an intrinsic overloaded" table as a bitfield.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Emit the intrinsic modref info as a lookup table instead of a huge switch.Benjamin Kramer
Shrinks BasicAliasAnalysis.o from 106k to 56k on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Implement getSubRegIndex as a linear search on the SubRegTable instead of ↵Benjamin Kramer
using a big switch. - The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts. - This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Tidy up. 80 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Tidy up. Spelling.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Move the subregister indicies enum into the REGINFO_ENUM section.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Switch TargetRegisterInfo::getSubReg() to use a lookup table.Jim Grosbach
Instead of nested switch statements, use a lookup table. On ARM, this replaces a 23k (x86_64 release build) function with a 16k table. Its not unlikely to be faster, as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Convert generated intrinsic attributes to use an array lookup as Chris ↵Craig Topper
suggested in PR11951. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper
Kay Tiong Khoo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that ↵Craig Topper
were added in r151038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151246 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Declare register classes as const. Fix a couple pointers to register classes ↵Craig Topper
that weren't already const. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151138 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper
to static data that should not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21Reorder some members in MCRegisterClass to remove padding on 64-bit builds.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21In generated RegisterInfo files, replace a pointer to the end of an array ↵Craig Topper
with just the size of the array to avoid relocations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21Merge some tables in generated RegisterInfo file. Store indices into larger ↵Craig Topper
table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19Add vmfunc instruction to X86 assembler and disassembler.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper
Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Make the EDis tables const.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer
This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer
pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Store just the SimpleValueType in the generated VT tables for each register ↵Benjamin Kramer
class, eliminating static ctors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per ↵Benjamin Kramer
entry on x86_64. No change on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150170 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy
UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09More tweaks to get the size of the X86 disassembler tables down.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper
needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Don't map registers to the invalid dwarf register (-1). It's the default value.Benjamin Kramer
X86GenRegisterInfo.inc | 1032 ------------------------------------------------- 1 file changed, 1032 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08Value initialize MCRegisterClasses. Not sure how could miss this during the ↵Benjamin Kramer
MCTargetDesc refactor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Convert assert(0) to llvm_unreachableCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Increment DFAStateEntryTable index for sentinel entry.Brendon Cahoon
When adding the {-1, -1} entry to the DFAStateInputTable, we need to increment the index used to populate the DFAStateEntryTable. Otherwise, the entry table will be off by one for each transition after the {-1, -1} entry. PR11908. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149713 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Specify SubRegIndex components on the index itself.Jakob Stoklund Olesen
It is simpler to define a composite index directly: def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>; def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>; Than specifying the composite indices on each register: CompositeIndices = [(ssub_2 dsub_1, ssub_0), (ssub_3 dsub_1, ssub_1)] in ... This also makes it clear that SubRegIndex composition is supposed to be unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Fix a bug in the TopoOrderRC comparison function.Jakob Stoklund Olesen
The final tie breaker comparison also needs to return +/-1, or 0. This is not a less() function. This could cause otherwise identical super-classes to be ordered unstably, depending on what the system qsort routine does with a bad compare function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149549 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Avoid emitting empty arrays, they're not standard C++.Jakob Stoklund Olesen
It's only by luck that we haven't produced any yet, and clang refuses to compile them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149546 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Don't assign a value to NUM_TARGET_NAMED_SUBREGS.Jakob Stoklund Olesen
It was wrong and completely unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149433 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Move the composite map into CodeGenSubRegIndex.Jakob Stoklund Olesen
Each SubRegIndex keeps track of how it composes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149423 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Add a TableGen CodeGenSubRegIndex class.Jakob Stoklund Olesen
This class is used to represent SubRegIndex instances instead of the raw Record pointers that were used before. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Tidy up. Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148856 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson
accomodate every target I can think of offhand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Add an (interleave A, B, ...) SetTheory operator.Jakob Stoklund Olesen
This will interleave the elements from two or more lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen
When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Add TableGen support for callee saved registers.Jakob Stoklund Olesen
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file. TableGen will use this to create a *_SaveList array suitable for returning from getCalleeSavedRegs() as well as a *_RegMask bit mask suitable for returning from getCallPreservedMask(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
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