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2012-06-06Round 2 of dead private variable removal.Benjamin Kramer
LLVM is now -Wunused-private-field clean except for - lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields. - gtest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: Added MultiIssueItineraries.Andrew Trick
This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-02Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Didn't mean to export this function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Emit register unit root tables.Jakob Stoklund Olesen
Each register unit has one or two root registers. The full set of registers containing a given register unit can be computed as the union of the root registers and their super-registers. Provide an MCRegUnitRootIterator class to enumerate the roots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Print uint16_t numbers without a sign.Jakob Stoklund Olesen
It seems I broke C++11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Remove little semicolon that caused a lot of warnings.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29Emit register unit lists for each register.Jakob Stoklund Olesen
Register units are already used internally in TableGen to compute register pressure sets and overlapping registers. This patch makes them available to the code generators. The register unit lists are differentially encoded so they can be reused for many related registers. This keeps the total size of the lists below 200 bytes for most targets. ARM has the largest table at 560 bytes. Add an MCRegUnitIterator for traversing the register unit lists. It provides an abstract interface so the representation can be changed in the future without changing all clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer
extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28switch AttrListPtr::get to take an ArrayRef, simplifying a lot of clients.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27rdar://11542750 - llvm.trap should be marked no return.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27Reimplement the intrinsic verifier to use the same table as ↵Chris Lattner
Intrinsic::getDefinition, making it stronger and more sane. Delete the code from tblgen that produced the old code. Besides being a path forward in intrinsic sanity, this also eliminates a bunch of machine generated code that was compiled into Function.o git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27move some code around so that Verifier.cpp can get access to the intrinsic ↵Chris Lattner
info table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27enhance the intrinsic info table to encode what *kind* of Any argumentChris Lattner
it is (at the cost of 45 bytes of extra table space) so that the verifier can start using it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-26rearrange some code, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25Compress MCRegisterInfo register name tables.Jakob Stoklund Olesen
Store (debugging) register names as offsets into a string table instead of as char pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157449 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24Teach tblgen's set theory "sequence" operator to support an optional stride ↵Owen Anderson
operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23Fixed typo in r156905.Patrik Hägglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23small refinement to r157218 to save a tiny amount of table size in the commonChris Lattner
case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-22Also compute TopoSigs in synthetic register classes.Jakob Stoklund Olesen
CodeGenRegisterClass has two constructors. Both need to compute the TopoSigs BitVector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157271 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-21Added address space qualifier to intrinsic PointerType arguments.Pete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17enhance the intrinsic info stuff to emit encodings that don't fit in 32-bits ↵Chris Lattner
into a separate side table, using the handy SequenceToOffsetTable class. This encodes all these weird things into another 256 bytes, allowing all intrinsics to be encoded this way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17finish encoding all of the interesting details of intrinsics. Now intrinsicsChris Lattner
are only rejected because they can't be encoded into a 32-bit unit, not because they contain an unencodable feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17strengthen the intrinsic descriptor stuff to be able to handle sin, cos and ↵Chris Lattner
other intrinsics that use passed-in arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156977 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17simplify code generated by tblgen that is not necessary since we droppedChris Lattner
compatibility with LLVM 2.x bitcode files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17I forgot the #ifdef _MSC_VER guard in my last commit.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156975 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17Fix the MSVC 2010 build: disable the optimizer for a problematic function.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156973 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16Use RegUnits to compute overlapping registers.Jakob Stoklund Olesen
TableGen already computes register units as the basic unit of interference. We can use that to compute the set of overlapping registers. This means that we can easily compute overlap sets for one register at a time. There is no benefit to computing all registers at once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16Significantly reduce the compiled size of Functions.cpp by turning a big ↵Chris Lattner
blob of tblgen generated code (for Intrinsic::getType) into a table. This handles common cases right now, but I plan to extend it to handle all cases and merge in type verification logic as well in follow-on patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156905 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16have tblgen emit cast<> instead of dyn_cast<> when we know it must succeed.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15TableGen'erate mapping physical registers to encoding values.Jim Grosbach
Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Create a struct representing register units in TableGen.Jakob Stoklund Olesen
Besides the weight, we also want to store up to two root registers per unit. Most units will have a single root, the leaf register they represent. Units created for ad hoc aliasing get two roots: The two aliasing registers. The root registers can be used to compute the set of overlapping registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Consider ad hoc aliasing when building RegUnits.Jakob Stoklund Olesen
Register units can be used to compute if two registers overlap: A overlaps B iff units(A) intersects units(B). With this change, the above holds true even on targets that use ad hoc aliasing (currently only ARM). This means that register units can be used to implement regsOverlap() more efficiently, and the register allocator can use the concept to model interference. When there is no ad hoc aliasing, the register units correspond to the maximal cliques in the register overlap graph. This is optimal, no other register unit assignment can have fewer units. With ad hoc aliasing, weird things are possible, and we don't try too hard to compute the maximal cliques. The current approach is always correct, and it works very well (probably optimally) as long as the ad hoc aliasing doesn't have cliques larger than pairs. It seems unlikely that any target would need more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156763 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Record the ad hoc aliasing graph in CodeGenRegister.Jakob Stoklund Olesen
The ad hoc aliasing specified in the 'Aliases' list in .td files is currently only used by computeOverlaps(). It will soon be needed to build accurate register units as well, so build the undirected graph in CodeGenRegister::buildObjectGraph() instead. Aliasing is a symmetric relationship with only one direction specified in the .td files. Make sure both directions are represented in getExplicitAliases(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Compute topological signatures of registers.Jakob Stoklund Olesen
TableGen creates new register classes and sub-register indices based on the sub-register structure present in the register bank. So far, it has been doing that on a per-register basis, but that is not very efficient. This patch teaches TableGen to compute topological signatures for registers, and use that to reduce the amount of redundant computation. Registers get the same TopoSig if they have identical sub-register structure. TopoSigs are not currently exposed outside TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12Speed up computeComposites() by using the new SubReg -> SubIdx map.Jakob Stoklund Olesen
TableGen doesn't need to search through the SubRegs map to find an inverse entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156690 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Remove extraneous ; and the resulting warning.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Defer computation of SuperRegs.Jakob Stoklund Olesen
Don't compute the SuperRegs list until the sub-register graph is completely finished. This guarantees that the list of super-registers is properly topologically ordered, and has no duplicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Compute secondary sub-registers.Jakob Stoklund Olesen
The sub-registers explicitly listed in SubRegs in the .td files form a tree. In a complicated register bank, it is possible to have sub-register relationships across sub-trees. For example, the ARM NEON double vector Q0_Q1 is a tree: Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3] But we also define the DPair register D1_D2 = [D1, D2] which is fully contained in Q0_Q1. This patch teaches TableGen to find such sub-register relationships, and assign sub-register indices to them. In the example, TableGen will create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a sub-register of Q0_Q1. This will eventually enable the coalescer to handle copies of skewed sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Precompute lists of explicit sub-registers and indices.Jakob Stoklund Olesen
The .td files specify a tree of sub-registers. Store that tree as ExplicitSubRegs lists in CodeGenRegister instead of extracting it from the Record when needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.Andrew Trick
I initially assumed that the subreg graph was a tree. That may not be true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09Fix warning text.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09Compute a backwards SubReg -> SubRegIndex map for each register.Jakob Stoklund Olesen
This mapping is for internal use by TableGen. It will not be exposed in the generated files. Unfortunately, the mapping is not completely well-defined. The X86 xmm registers appear with multiple sub-register indices in the ymm registers. This is because of the odd idempotent sub_sd and sub_ss sub-register indices. I hope to be able to eliminate them entirely, so we can require the sub-registers to form a tree. For now, just place the canonical sub_xmm index in the mapping, and ignore the idempotents. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-09Rename getSubRegs() to computeSubRegs().Jakob Stoklund Olesen
That's what it does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06TableGen: AsmMatcher diagnostic when missing instruction mnemonic.Jim Grosbach
Previously, if an instruction definition was missing the mnemonic, the next line would just assert(). Issue a real diagnostic instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Order register classes by spill size first, members last.Jakob Stoklund Olesen
This is still a topological ordering such that every register class gets a smaller enum value than its sub-classes. Placing the smaller spill sizes first makes a difference for the super-register class bit masks. When looking for a super-register class, we usually want the smallest possible kind of super-register. That is now available as the first bit set in the bit mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen
This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen
TargetRegisterClass now gives access to the necessary tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Add TargetRegisterClass::getSuperRegIndices().Jakob Stoklund Olesen
This is a pointer into one of the tables used by getMatchingSuperRegClass(). It makes it possible to use a shared implementation of that function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8
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