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2010-11-18Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim
.o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18Give the exclamation point a name instead of a number.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18Change the 'x' type modifier for Neon intrinsics to force a signed integer.Bob Wilson
This makes it symmetric with the 'u' modifier that forces an unsigned type. This is needed for unsigned vector shifts, where the shift amount still needs to be signed. PR8482 (Radar 8603521). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling
instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Use new neon_vector_type and neon_polyvector_type attributes for Neon vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Change Neon polynomial types to be signed to match GCC.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Refactor to new GetNumElements function.Bob Wilson
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119404 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Tidy up some things in <arm_neon.h>.Bob Wilson
Stop defining types with "__neon_" prefixes and then using typedefs without the prefix; there's no reason to do that anymore. Remove types that combine multiple Neon vectors and treat them as a single long vector; they are not used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Reapply "Stop using struct wrappers for Neon vector types in <arm_neon.h>."Bob Wilson
I've temporarily disabled the failing clang test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Revert "Stop using struct wrappers for Neon vector types in <arm_neon.h>."Bob Wilson
It's breaking buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119363 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Stop using struct wrappers for Neon vector types in <arm_neon.h>.Bob Wilson
Thanks to Nate Begeman for an earlier version of this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling
'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15pull the code to get the operand value out of the loop.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15split the giant encoder loop into two new helper functions.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119129 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15reduce nesting and minor cleanups, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner
Switch the ARM backend to use 'let' instead of 'set' with this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11ARM fixup encoding for direct call instructions (BL).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Add support for specifying a PostEncoderMethod, which can perform ↵Owen Anderson
post-processing after the automated encoding of an instruction. Not yet used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10Rename AccessesArguments and AccessesArgumentsReadonly, and rewriteDan Gohman
their comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Translate IntrReadArgMem to AccessesArgumentsReadonly.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06pass literals like $$1 through to the asm matcher. This isn't right yet, ↵Chris Lattner
but doesn't hurt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06add (and document) the ability for alias results to haveChris Lattner
fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06generalize alias support to allow the result of an alias toChris Lattner
add fixed immediate values. Move the aad and aam aliases to use this, and document it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06fix a bug where we had an implicit assumption that theChris Lattner
result instruction operand numbering matched the result pattern. Fixing this allows us to move the xchg/test aliases to the .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06fix some bugs in the alias support, unblocking changing of "clr" aliasesChris Lattner
from c++ hacks to proper .td InstAlias definitions. Change them! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06Reimplement BuildResultOperands to be in terms of the result instruction'sChris Lattner
operand list instead of the operand list redundantly declared on the alias or instruction. With this change, we finally remove the ins/outs list on the alias. Before: def : InstAlias<(outs GR16:$dst), (ins GR8 :$src), "movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; After: def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>; This also makes the alias mechanism more general and powerful, which will be exploited in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06implement more checking to reject things like:Chris Lattner
(someinst GR16:$foo, GR32:$foo) Reimplement BuildAliasOperandReference to be correctly based on the names of operands in the result pattern, instead of on the instruction operand definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118328 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06decode and validate instruction alias result definitions.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06simplifyChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118326 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06fix another fixme, replacing a string with a semantic pointer.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06disolve a hack, having CodeGenInstAlias decode the alias in the .tdChris Lattner
file instead of the asmmatcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04In the calling convention logic, ValVT is always a legal type,Duncan Sands
and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04partition operand processing between aliases and instructions.Chris Lattner
Right now the code is partitioned but the behavior is the same. This should be improved in the near future. This removes some uses of TheOperandList. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04pull name slicing out of BuildInstructionOperandReference soChris Lattner
it doesn't do any lexical stuff anymore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04cleanups.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04replace SrcOpNum with SrcOpName, eliminating a numering dependencyChris Lattner
on the incoming operand list. This also makes the code simpler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04strength reduce some code, resolving a fixme.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04take a big step to making aliases more general and less of a hack:Chris Lattner
now matchables contain an explicit list of how to populate each operand in the result instruction instead of having them somehow magically be correlated to the input inst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Support generating an MC'ized CodeEmitter directly. Maintain a reference to theJim Grosbach
Fixups list for the instruction so the operand encoders can add to it as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03rename Operand -> AsmOperand for clarity.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Inside the calling convention logic LocVT is always a simpleDuncan Sands
value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach
parts. Represent the operation mode as an optional operand instead. rdar://8614429 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Completely reject instructions that have an operand in theirChris Lattner
ins/outs list that isn't specified by their asmstring. Previously the asmmatcher would just force a 0 register into it, which clearly isn't right. Mark a bunch of ARM instructions that use this as isCodeGenOnly. Some of them are clearly pseudo instructions (like t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will either need to be removed or the asmmatcher will need to be taught about it (someday). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02make MatchableInfo::Validate reject instructions (like LDR_PRE in ARM)Chris Lattner
that have complicated tying going on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02rewrite EmitConvertToMCInst to iterate over the MCInst operands,Chris Lattner
filling them in one at a time. Previously this iterated over the asmoperands, which left the problem of "holes". The new approach simplifies things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02merge two large parallel loops in EmitConvertToMCInst, no changeChris Lattner
in the generated .inc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02a bunch of random cleanup, move a helper to CGT where it belongs.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach
assumptions about stack layout. Specifically, LR must be saved next to FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02add and update comments.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118025 91177308-0d34-0410-b5e6-96231b3b80d8
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