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2012-09-06Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem
allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Constify subtarget info properly so that we dont cast away the const inRoman Divacky
the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Fix function name per coding standard.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163187 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Fix function name per coding standard.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163186 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Make comment more verbose and add an assert.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163125 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, addChad Rosier
the NumMCOperands argument to the GetMCInstOperandNum() function that is set to the number of MCOperands this asm operand mapped to. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Add an interface to the GetMCInstOperandNum() function in theChad Rosier
MCTargetAsmParser class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Remove extraneous return.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163119 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Return the MCOperandNum instead of passing a reference.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Removed unused argument.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Expose the Kind and Opcode variables from theChad Rosier
MatchInstructionImpl() function. These values are used by the ConvertToMCInst() function to index into the ConversionTable. The values are also needed to call the GetMCInstOperandNum() function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()Chad Rosier
function nowadays. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Add support for converting llvm.fma to fma4 instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31With the fix in r162954/162955 every cvt function returns true. Thus, haveChad Rosier
the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Hoist a check to eliminate obvious mismatches as early as possible. Also, fixChad Rosier
an 80-column violation in the generated code. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162944 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30[ms-inline asm] Add a new function, GetMCInstOperandNum, to theChad Rosier
AsmMatcherEmitter. This function maps inline assembly operands to MCInst operands. For example, '__asm mov j, eax' is represented by the follow MCInst: <MCInst 1460 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand Expr:(j)> <MCOperand Reg:0> <MCOperand Reg:43>> The first 5 MCInst operands are a result of j matching as a memory operand consisting of a BaseReg (Reg:0), MemScale (Imm:1), MemIndexReg(Reg:0), Expr (Expr:(j), and a MemSegReg (Reg:0). The 6th MCInst operand represents the eax register (Reg:43). This translation is necessary to determine the Input and Output Exprs. If a single asm operand maps to multiple MCInst operands, the index of the first MCInst operand is returned. Ideally, it would return the operand we really care out (i.e., the Expr:(j) in this case), but I haven't found an easy way of doing this yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162920 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29Fix a nondeterminism in the ARM assembler.Andrew Trick
Adding arbitrary records to ARM.td would break basic-arm-instructions.s because selection of nop vs mov r0,r0 was ambiguous (this will be tested by a subsequent addition to ARM.td). An imperfect but sensible fix is to give precedence to match rules that have more constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Check all patterns for missing instruction flags.Jakob Stoklund Olesen
Both single-instruction and multi-instruction patterns can be checked for missing mayLoad / mayStore, and hasSideEffects flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith
Reviewed offline by chandlerc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Infer instruction properties from single-instruction patterns.Jakob Stoklund Olesen
Previously, instructions without a primary patterns wouldn't get their properties inferred. Now, we use all single-instruction patterns for inference, including 'def : Pat<>' instances. This causes a lot of instruction flags to change. - Many instructions no longer have the UnmodeledSideEffects flag because their flags are now inferred from a pattern. - Instructions with intrinsics will get a mayStore flag if they already have UnmodeledSideEffects and a mayLoad flag if they already have mayStore. This is because intrinsics properties are linear. - Instructions with atomic_load patterns get a mayStore flag because atomic loads can't be reordered. The correct workaround is to create pseudo-instructions instead of using normal loads. PR13693. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Stop inferring isVariadic from instruction patterns.Jakob Stoklund Olesen
Instructions are now only marked as variadic if they use variable_ops in their ins list. A variadic SDNode is typically used for call nodes that have the call arguments as operands. A variadic MachineInstr can actually encode a variable number of operands, for example ARM's stm/ldm instructions. A call instruction does not have to be variadic. The call argument registers are added as implicit operands. This change remove the MCID::Variadic flags from most call and return instructions, allowing us to better verify their operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Verify explicit instruction properties when they can be inferred.Jakob Stoklund Olesen
It is now allowed to explicitly set hasSideEffects, mayStore, and mayLoad on instructions with patterns. Verify that the patterns are consistent with the explicit flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Heed guessInstructionProperties, and stop warning on redundant flags.Jakob Stoklund Olesen
Emit TableGen errors if guessInstructionProperties is 0 and instruction properties can't be inferred from patterns. Allow explicit instruction properties even when they can be inferred. This patch doesn't change the TableGen output. Redundant properties are not yet verified because the tree has errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Tristate mayLoad, mayStore, and hasSideEffects.Jakob Stoklund Olesen
Keep track of the set/unset state of these bits along with their true/false values, but treat '?' as '0' for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Add CodeGenTarget::guessInstructionProperties.Jakob Stoklund Olesen
Currently, TableGen just guesses instruction properties when it can't infer them form patterns. This adds a guessInstructionProperties flag to the instruction set definition that will be used to disable guessing. The flag is intended as a migration aid. It will be removed again when no more targets need their properties guessed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Fix a bunch of -Wdocumentation warnings.Dmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162446 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Print out the location of expanded multiclass defs in TableGen errors.Jakob Stoklund Olesen
When reporting an error for a defm, we would previously only report the location of the outer defm, which is not always where the error is. Now we also print the location of the expanded multiclass defs: lib/Target/X86/X86InstrSSE.td:2902:12: error: foo defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>, ^ lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128, ^ lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22TblGen: Make asm-matcher ConvertToMCInst() table driven.Jim Grosbach
No change in interface or functionality. Purely under-the-hood details of the generated function that change. The X86 assembly parser is reduced in size by over 15% and ARM by over 10%. No performance change by my measurements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162337 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-21Formatting. No functional change.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Add stub methods for mips assembly matcher. Akira Hatanaka
Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Declare some for loop indices inside the for loop statement.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162085 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Fix up indentation of outputted decode function for readability.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen
Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Add a CoveringSubRegIndices field to SubRegIndex records.Jakob Stoklund Olesen
This can be used to tell TableGen to use a specific SubRegIndex instead of synthesizing one when discovering all sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Make synthesized sub-register indexes available in the target namespace.Jakob Stoklund Olesen
TableGen sometimes synthesizes missing sub-register indexes. Emit these indexes as enumerators in the target namespace along with the user-defined ones. Also take this opportunity to stop creating new Record objects for synthetic indexes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161964 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Fix a const violation in the generated disassembler.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161940 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14Switch the fixed-length disassembler to be table-driven.Jim Grosbach
Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10Add some missing includes for the build against stdcxx.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08Added MispredictPenalty to SchedMachineModel.Andrew Trick
This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Remove extraneous ';'.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper
used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Use uint8_t to store the InstructionContext table. Saves 768 bytes of static ↵Craig Topper
data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Tidy up. Move for loop index declarations into for statements. Use unsigned ↵Craig Topper
instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Tidy up function argument formatting.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Remove trailing whitespaceCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Remove trailing whitespaceCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The ↵Craig Topper
isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30Remove some unnecessary filter checks. They were already covered by ↵Craig Topper
IsCodeGenOnly git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160950 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-25 03:26:18 +0000