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path: root/utils/TableGen/CodeGenTarget.cpp
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2010-08-05Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMemDan Gohman
to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling
thus is a much more meaningful name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen
The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen
list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Add StringRef::compare_numeric and use it to sort TableGen register records.Jakob Stoklund Olesen
This means that our Registers are now ordered R7, R8, R9, R10, R12, ... Not R1, R10, R11, R12, R2, R3, ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen
structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13Adding a v8i64 512-bit vector type. This will be used to model ARM NEON ↵Evan Cheng
intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng
sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27fix CodeGenTarget::getRegisterVTs to not return the Chris Lattner
same vt multiple times for a register. For example, ECX is in 5 different i32 reg classes, just return 1 i32 instead of 5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23reject void in intrinsic type lists.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22Change intrinsic result type for void to store it as an empty listChris Lattner
instead of as a single element list with VoidTy. Now with a fix for the verifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19Revert r99009 temporarily it seems to be breaking the bots.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99011 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19Change intrinsic result type for void to store it as an empty listChris Lattner
instead of as a single element list with VoidTy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19add a new SDNPVariadic SDNP node flag, and use it inChris Lattner
dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19Finally change the instruction looking map to be a densemap fromChris Lattner
record* -> instrinfo instead of std::string -> instrinfo. This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug build (20%). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner
Use CodeGenTarget::getInstNamespace in one place and fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19revert 98912Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19change Target.getInstructionsByEnumValue to return a referenceChris Lattner
to a vector that CGT stores instead of synthesizing it on every call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19factor copy and paste code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98908 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19look up instructions by record, not by name.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-15Completely rewrite tblgen's type inference mechanism,Chris Lattner
changing the primary datastructure from being a "std::vector<unsigned char>" to being a new TypeSet class that actually has (gasp) invariants! This changes more things than I remember, but one major innovation here is that it enforces that named input values agree in type with their output values. This also eliminates code that transparently assumes (in some cases) that SDNodeXForm input/output types are the same, because this is wrong in many case. This also eliminates a bug which caused a lot of ambiguous patterns to go undetected, where a register class would sometimes pick the first possible type, causing an ambiguous pattern to get arbitrary results. With all the recent target changes, this causes no functionality change! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09move target-independent opcodes out of TargetInstrInfoChris Lattner
into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen
Also, DEBUG_VALUE has side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-09Add DEBUG_DECLARE. Not used yet.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-08Add DEBUG_VALUE. Not used yet.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-04Remove the CPAttrParentAsRoot code, which is unused, and inconvenientDan Gohman
for a refactoring I'm working on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92503 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen
unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson
while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Fix a few more places in TableGen that need to handle EVT::vAny types.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78643 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsicBob Wilson
arguments that are vectors of any size and element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson
own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Match X86 register names to number.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15Remove the v3i32 and v3f32 value types: they are notDuncan Sands
native for any supported targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75785 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14Revert 75308.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75565 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10Add new vector types for 192-bit, 348-bit and 512-bit sizes.Bob Wilson
These are needed to represent ARM Neon struct datatypes containing 2, 3 or 4 separate vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75308 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10Refactor TableGen's llvm::getName to share code with llvm::getEnumName,Bob Wilson
since names are the same for almost all the types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75302 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-06Add new ValueType for metadata.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74882 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar
- Sorry, I can't help myself. - No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29Add more vector ValueTypes for AVX and other extended vector instructionDavid Greene
sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74427 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02Revert 72707 and 72709, for the moment.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01Make the implicit inputs and outputs of target-independentDale Johannesen
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16Fix PR3994: LLVMMatchType arguments do not refer to absolute return valueBob Wilson
and argument positions but only to the overloaded intrinsic parameters. Keep a separate list of these overloaded parameters in CodeGenTarget.cpp so they can be resolved easily. Remove assertions from IntrinsicEmitter.cpp: they were harmless but confusing, and the assertions elsewhere in TableGen will catch any incorrect values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69316 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman
it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman
This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05Reapply 63765. Patches for clang and llvm-gcc to follow.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04Reverting 63765. This broke the build of both clangDale Johannesen
and llvm-gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04New feature: add support for target intrinsics being defined in theNate Begeman
target directories themselves. This also means that VMCore no longer needs to know about every target's list of intrinsics. Future work will include converting the PowerPC target to this interface as an example implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-12add nocapture attribute to llvm.mem* intrinsics and have tblgenChris Lattner
parse them. tblgen doesn't yet do anything with this info though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62065 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07Improve support for type-generic vector intrinsics by teaching TableGen howBob Wilson
to handle LLVMMatchType intrinsic parameters, and by adding new subclasses of LLVMMatchType to match vector types with integral elements that are either twice as wide or half as wide as the elements of the matched type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61834 91177308-0d34-0410-b5e6-96231b3b80d8
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