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path: root/utils/TableGen/CodeGenTarget.cpp
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2012-03-01Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach
This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Convert assert(0) to llvm_unreachableCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Added MVT::v2f16Pete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel
AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add basic generic CodeGen support for half.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06First chunk of MachineInstr bundle support.Evan Cheng
1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne
This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen
This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Unconstify InitsDavid Greene
Remove const qualifiers from Init references, per Chris' request. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29[AVX] Constify InitsDavid Greene
Make references to Inits const everywhere. This is the final step before making them unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher
in multiple buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11[AVX] Make Inits FoldableDavid Greene
Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Add support for alternative register names, useful for instructions whose ↵Owen Anderson
operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen
Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Fix formatting.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson
features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen
Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen
No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen
Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen
Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Move TableGen's register bank classes to their own source file.Jakob Stoklund Olesen
I'll be moving some more code there to gather all of the register-specific stuff in one place. Currently it is shared between CodeGenTarget and RegisterInfoEmitter. The plan is that CodeGenRegisters can compute the full register bank structure while RegisterInfoEmitter only will handle the printing part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Make it possible to have unallocatable register classes.Jakob Stoklund Olesen
Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Change how tblgen generates attributes for intrinsics to use a singleJohn McCall
switch. With this newfound organization, teach tblgen how not to give all intrinsics the 'nounwind' attribute. Introduce a new intrinsic, llvm.eh.resume, which does not have this attribute. Documentation and uses to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07Teach TableGen to automatically generate missing SubRegIndex instances.Jakob Stoklund Olesen
The RegisterInfo.td file should only specify the indexes that sources need to refer to. The rest is inferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Don't allow per-register spill size and alignment.Jakob Stoklund Olesen
These values were not used for anything. Spill size and alignment is a property of the register class, not the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen
On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Make the register enum value part of the CodeGenRegister struct.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Flag -> Glue, the ongoing sagaChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner
something that just glues two nodes together, even if it is sometimes used for flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15various cleanups to tblgen, patch by Garrison Venn!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121837 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13eliminate the Records global variable, patch by Garrison Venn!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02a bunch of random cleanup, move a helper to CGT where it belongs.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01eliminate the old InstFormatName which is always "AsmString",Chris Lattner
simplify CodeGenInstruction. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21fix a long standing wart: all the ComplexPattern's were beingChris Lattner
passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07Add an MVT::x86mmx type. It will take the place of all current MMX vector types.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113261 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07Fix whitespace, because I'm OCD.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113250 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMemDan Gohman
to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling
thus is a much more meaningful name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen
The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen
list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26Add StringRef::compare_numeric and use it to sort TableGen register records.Jakob Stoklund Olesen
This means that our Registers are now ordered R7, R8, R9, R10, R12, ... Not R1, R10, R11, R12, R2, R3, ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen
structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13Adding a v8i64 512-bit vector type. This will be used to model ARM NEON ↵Evan Cheng
intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng
sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27fix CodeGenTarget::getRegisterVTs to not return the Chris Lattner
same vt multiple times for a register. For example, ECX is in 5 different i32 reg classes, just return 1 i32 instead of 5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23reject void in intrinsic type lists.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22Change intrinsic result type for void to store it as an empty listChris Lattner
instead of as a single element list with VoidTy. Now with a fix for the verifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99206 91177308-0d34-0410-b5e6-96231b3b80d8
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