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path: root/utils/TableGen/CodeGenRegisters.cpp
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2012-04-18tblgen: remove duplicated newlines.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155038 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Move a few more warnings to use PrintWarning().Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11TableGen'd regpressure: register unit set pruning.Andrew Trick
The pruning is more complete if it is not done incrementally. The code is also a tad less convluted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Table-generated register pressure fixes.Andrew Trick
Handle mixing allocatable and unallocatable register gracefully. Simplify the pruning of register unit sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154474 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10TableGen/reginfo potential bug: typo from previous checkin.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154452 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Fix for register pressure tables.Andrew Trick
Recent refactoring introduced a bug. Fix: added buildRegUnitSets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Use std::includes instead of my own implementation.Andrew Trick
Jakob's review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154377 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Added register unit sets to the target description.Andrew Trick
This is a new algorithm that finds sets of register units that can be used to model registers pressure. This handles arbitrary, overlapping register classes. Each register class is associated with a (small) list of pressure sets. These are the dimensions of pressure affected by the register class's liveness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154374 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Added register unit weights to the target description.Andrew Trick
This is a new algorithm that associates registers with weighted register units to accuretely model their effect on register pressure. This handles registers with multiple overlapping subregisters. It is possible, but almost inconceivable that the algorithm fails to find an exact solution for a target description. If an exact solution cannot be found, an inexact, but reasonable solution will be chosen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03Cleanup set_union usage. The same thing but a bit cleaner now.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-03Use std::set_union instead of nasty custom code.Andrew Trick
I just noticed Jakob's examples of the proper application of std::set... routines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31comment typoAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153796 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Introduce Register Units: Give each leaf register a number.Andrew Trick
First small step toward modeling multi-register multi-pressure. In the future, register units can also be used to model liveness and aliasing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Add more constness to CodeGenRegisters.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Specify SubRegIndex components on the index itself.Jakob Stoklund Olesen
It is simpler to define a composite index directly: def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>; def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>; Than specifying the composite indices on each register: CompositeIndices = [(ssub_2 dsub_1, ssub_0), (ssub_3 dsub_1, ssub_1)] in ... This also makes it clear that SubRegIndex composition is supposed to be unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Fix a bug in the TopoOrderRC comparison function.Jakob Stoklund Olesen
The final tie breaker comparison also needs to return +/-1, or 0. This is not a less() function. This could cause otherwise identical super-classes to be ordered unstably, depending on what the system qsort routine does with a bad compare function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149549 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Move the composite map into CodeGenSubRegIndex.Jakob Stoklund Olesen
Each SubRegIndex keeps track of how it composes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149423 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Add a TableGen CodeGenSubRegIndex class.Jakob Stoklund Olesen
This class is used to represent SubRegIndex instances instead of the raw Record pointers that were used before. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen
When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Add TableGen support for callee saved registers.Jakob Stoklund Olesen
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file. TableGen will use this to create a *_SaveList array suitable for returning from getCalleeSavedRegs() as well as a *_RegMask bit mask suitable for returning from getCallPreservedMask(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13Skip the NAME field when forming tuples.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148147 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13Delete CodeInit and CodeRecTy from TableGen.Jakob Stoklund Olesen
The code type was always identical to a string anyway. Now it is simply a synonym. The code literal syntax [{...}] is still valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen
Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19Synthesize register classes for TRI::getMatchingSuperRegClass().Jakob Stoklund Olesen
Teach TableGen to create the missing register classes needed for getMatchingSuperRegClass() to return maximal results. The function is still not auto-generated, so it still returns inexact results. This produces these new register classes: ARM: QQPR_with_dsub_0_in_DPR_8 QQQQPR_with_dsub_0_in_DPR_8 X86: GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP GR64_with_sub_16bit_in_GR16_NOREX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_with_sub_32bit_in_GR32_TC GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC GR64_with_sub_32bit_in_GR32_AD GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX The other targets in the tree are not weird enough to be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16Extract a method. No functional change.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Use the proper comparator for set_intersection.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Synthesize missing register class intersections.Jakob Stoklund Olesen
The function TRI::getCommonSubClass(A, B) returns the largest common sub-class of the register classes A and B. This patch teaches TableGen to synthesize sub-classes such that the answer is always maximal. In other words, every register that is in both A and B will also be present in getCommonSubClass(A, B). This introduces these synthetic register classes: ARM: GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR tGPR_and_tcGPR hGPR_and_tcGPR X86: GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR64_NOSP_and_GR64_TC GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_TC GR32_NOAX_and_GR32_NOSP GR64_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_ABCD_and_GR32_NOAX GR64_ABCD_and_GR64_TC GR32_NOAX_and_GR32_TC GR32_AD_and_GR32_NOAX Other targets are unaffected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12Extract a method.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146374 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen
This function is used to constrain a register class to a sub-class that supports the given sub-register index. For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD. The function will be used to compute register classes when emitting INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation of sub-register operations. The version provided by TableGen is usually adequate, but targets can override. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Properly use const_iterator.Jakob Stoklund Olesen
This should unbreak the Windows build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Teach TableGen to infer missing register classes.Jakob Stoklund Olesen
The set of register classes should be closed under sub-register operations and intersections. That will allow the register allocator to model combinations of constraints accurately. This patch implements the easiest form of register class inference: For every register class, and for every sub-register SubIdx, the subset of registers in RC that have a SubIdx sub-register should also be a register class. This does create some new register classes for the targets in the tree: ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td file on purpose because it only has two registers. InstrEmitter and RegisterCoalescer have safeguards against selecting too small register classes, so it is harmless. PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32 sub-register of LR8. I think that might be an omission? X86 puts RIP in the GR64 class, and since that register doesn't have 8-bit sub-registers, we get: GR64_with_sub_8bit GR64_TC_with_sub_8bit GR64_NOREX_with_sub_8bit GR64_TC_with_sub_8bit_hi The various CodeGen classes have already been fixed so adding new register classes should not affect compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Store all allocation orders together.Jakob Stoklund Olesen
There is no need to keep the primary order separate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen
When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04TableGen: Don't add synthetic Records to the RecordKeeper.Jakob Stoklund Olesen
The RecordKeeper could be shared by multiple target instances, causing duplicate record errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne
This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().Jakob Stoklund Olesen
All the sub-class bit vectors are computed when first creating the register bank. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Compute lists of super-classes in CodeGenRegisterClass.Jakob Stoklund Olesen
Use these lists instead of computing them on the fly in RegisterInfoEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Precompute a bit vector of register sub-classes.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140827 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30Order register classes topologically.Jakob Stoklund Olesen
All register classes are given a lower ID than their sub-classes. Cliques are ordered alphabetically. This will be used to simplify some sub-class operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen
This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Unconstify InitsDavid Greene
Remove const qualifiers from Init references, per Chris' request. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29[AVX] Create Inits Via Factory MethodDavid Greene
Replace uses of new *Init with *Init::get. This hides the allocation implementation so that we can unique Inits in various ways. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29[AVX] Constify InitsDavid Greene
Make references to Inits const everywhere. This is the final step before making them unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Intern all RecTy subclass instances to avoid duplicates.Jakob Stoklund Olesen
Make all of the RecTy constructors private, and use get() factory methods instead. Return singleton instances when it makes sense. ListTy instance pointers are stored in the element RecTy instance. BitsRecTy instance pointers, one per length, are stored in a static vector. Also unique DefInit instances. A Record has a unique DefInit which has a unique RecordRecTy instance. This saves some 200k-300k RecTy allocations when parsing ARM.td. It reduces TableGen's heap usage by almost 50%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher
in multiple buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Use get(0 Instead of Create()David Greene
Respond to some feedback asking for a name change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11[AVX] Make Inits FoldableDavid Greene
Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Consolidate some TableGen diagnostic helper functions.Jim Grosbach
TableGen had diagnostic printers sprinkled about in a few places. Pull them together into a single location in Error.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Skip fields that don't exist in the Register class.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133470 91177308-0d34-0410-b5e6-96231b3b80d8
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