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path: root/utils/TableGen/CodeEmitterGen.cpp
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2012-03-09TableGen/CodeEmitterGen.cpp: Fix an expression of generating bitmask.NAKAMURA Takumi
~0U might be i32 on 32-bit hosts, then (uint64_t)~0U might not be expected as (i64)0xFFFFFFFF_FFFFFFFF, but as (i64)0x00000000_FFFFFFFF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152407 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Fix support for encodings up to 64-bits in length. TableGen was silently ↵Owen Anderson
truncating them to 32-bits prior to this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson
accomodate every target I can think of offhand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Move TableGen's parser and entry point into a libraryPeter Collingbourne
This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Unconstify InitsDavid Greene
Remove const qualifiers from Init references, per Chris' request. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29[AVX] Create Inits Via Factory MethodDavid Greene
Replace uses of new *Init with *Init::get. This hides the allocation implementation so that we can unique Inits in various ways. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29[AVX] Constify InitsDavid Greene
Make references to Inits const everywhere. This is the final step before making them unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29[AVX] Remove Mutating Members from InitsDavid Greene
Get rid of all Init members that modify internal state. This is in preparation for making references to Inits const. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Revert r134921, 134917, 134908 and 134907. They're causing failuresEric Christopher
in multiple buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Use get(0 Instead of Create()David Greene
Respond to some feedback asking for a name change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11[AVX] Make Inits FoldableDavid Greene
Manage Inits in a FoldingSet. This provides several benefits: - Memory for Inits is properly managed - Duplicate Inits are folded into Flyweights, saving memory - It enforces const-correctness, protecting against certain classes of bugs The above benefits allow Inits to be used in more contexts, which in turn provides more dynamism to TableGen. This enhanced capability will be used by the AVX code generator to a fold common patterns together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06Don't require pseudo-instructions to carry encoding information.Jim Grosbach
For now this is distinct from isCodeGenOnly, as code-gen-only instructions can (and often do) still have encoding information associated with them. Once we've migrated all of them over to true pseudo-instructions that are lowered to real instructions prior to the printer/emitter, we can remove isCodeGenOnly and just use isPseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Fix a bug in tblgen that caused incorrect encodings on instructions that ↵Owen Anderson
specified operands with "bit" instead of "bits<1>". Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question. <rdar://problem/9345702> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130410 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-03Tidy up a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Fix a comment typo.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin
new gcc warning that complains on self-assignments and self-initializations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13Move <map> include out of .h and into .cpp.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13eliminate the Records global variable, patch by Garrison Venn!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15pull the code to get the operand value out of the loop.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15split the giant encoder loop into two new helper functions.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119129 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15reduce nesting and minor cleanups, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner
Switch the ARM backend to use 'let' instead of 'set' with this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Add support for specifying a PostEncoderMethod, which can perform ↵Owen Anderson
post-processing after the automated encoding of an instruction. Not yet used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Support generating an MC'ized CodeEmitter directly. Maintain a reference to theJim Grosbach
Fixups list for the instruction so the operand encoders can add to it as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach
assumptions about stack layout. Specifically, LR must be saved next to FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01factor the operand list (and related fields/operations) out of Chris Lattner
CodeGenInstruction into its own helper class. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12Allow targets to optionally specify custom binary encoder functions forJim Grosbach
operand values. This is useful for operands which require additional trickery to encode into the instruction. For example, the ARM shifted immediate and shifted register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11The assert() should reference to machine instr operand number, too.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11Make sure to use the machine instruction operand number. It doesn't alwaysJim Grosbach
map one-to-one with the CodeGenInstruction operand number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11When figuring out which operands match which encoding fields in an instruction,Jim Grosbach
try to match them by name first. If there is no by-name match, fall back to assuming they are in order (this was the previous behavior). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen
list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng
sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07rename llvm::llvm_report_error -> llvm::report_fatal_errorChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19change Target.getInstructionsByEnumValue to return a referenceChris Lattner
to a vector that CGT stores instead of synthesizing it on every call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19look up instructions by record, not by name.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09move target-independent opcodes out of TargetInstrInfoChris Lattner
into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen
Also, DEBUG_VALUE has side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-09Add DEBUG_DECLARE. Not used yet.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-08Add DEBUG_VALUE. Not used yet.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15Revert 90628, which was incorrect.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91448 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05Minor code simplification.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90628 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen
unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08Convert more abort() calls to llvm_report_error().Torok Edwin
Also remove trailing semicolon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75027 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar
- Sorry, I can't help myself. - No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman
it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman
This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-05Fix shift overflow bug that would occur when a field was a full 32-bits Chris Lattner
in tblgen. This is PR2827, thanks to Waldemar Knorr for tracking this down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57124 91177308-0d34-0410-b5e6-96231b3b80d8
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