| Age | Commit message (Expand) | Author |
|---|
| 2011-07-29 | Unconstify Inits | David Greene |
| 2011-07-29 | [AVX] Constify Inits | David Greene |
| 2011-07-21 | Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n... | Owen Anderson |
| 2011-07-18 | Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple... | Owen Anderson |
| 2011-07-18 | Re-apply r135319 with a fix for the constant island pass. | Owen Anderson |
| 2011-07-16 | Revert r135319 in an attempt to get to unbreak testers. | Owen Anderson |
| 2011-07-15 | Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tB... | Owen Anderson |
| 2011-07-11 | Revert r134921, 134917, 134908 and 134907. They're causing failures | Eric Christopher |
| 2011-07-11 | [AVX] Make Inits Foldable | David Greene |
| 2011-07-06 | Don't require pseudo-instructions to carry encoding information. | Jim Grosbach |
| 2011-06-30 | Pseudo-ize the Thumb tTPsoft instruction. | Jim Grosbach |
| 2011-06-30 | Pseudo-ize the Thumb tPOP_RET instruction. | Jim Grosbach |
| 2011-06-29 | Remove redundant Thumb2 ADD/SUB SP instruction definitions. | Jim Grosbach |
| 2011-06-29 | ARM RSCS* don't need explicit TableGen decoder checks. | Jim Grosbach |
| 2011-06-29 | Refactor away tSpill and tRestore pseudos in ARM backend. | Jim Grosbach |
| 2011-04-22 | Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) s... | Johnny Chen |
| 2011-04-15 | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner |
| 2011-04-11 | Thumb disassembler was erroneously rejecting "blx sp" instruction. | Johnny Chen |
| 2011-03-25 | delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ins... | Johnny Chen |
| 2011-03-24 | The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ... | Johnny Chen |
| 2011-03-24 | The ARM disassembler was confused with the 16-bit tSTMIA instruction. | Johnny Chen |
| 2011-03-24 | ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder wa... | Johnny Chen |
| 2011-03-12 | Remove no-longer-correct special case for disasm of ARM BL instructions. | Jim Grosbach |
| 2011-03-11 | Pseudo-ize the ARM 'B' instruction. | Jim Grosbach |
| 2011-03-11 | Remove dead code. These ARM instruction definitions no longer exist. | Jim Grosbach |
| 2011-03-11 | Remove dead code. These ARM instruction definitions no longer exist. | Jim Grosbach |
| 2011-03-11 | Pseudo-ize VMOVDcc and VMOVScc. | Jim Grosbach |
| 2011-03-11 | Remove dead code. These ARM instruction definitions don't exist. | Jim Grosbach |
| 2011-03-11 | ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same | Jim Grosbach |
| 2011-03-11 | Remove dead code. These ARM instruction definitions don't exist. | Jim Grosbach |
| 2011-03-11 | ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q | Jim Grosbach |
| 2011-03-11 | ARM VREV64df and VREV64qf can just be patterns. The instruction is the same | Jim Grosbach |
| 2011-03-11 | Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos. | Jim Grosbach |
| 2011-03-10 | Properly pseudo-ize MOVCCr and MOVCCs. | Jim Grosbach |
| 2011-03-10 | Memory barrier instructions don't need special handling in tblgen anymore. | Jim Grosbach |
| 2011-03-03 | TableGen should not ignore BX instructions for the ARM disassembler. pr9368. | Bob Wilson |
| 2011-03-03 | pr9367: Add missing predicated BLX instructions. | Bob Wilson |
| 2011-02-18 | Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fi... | Owen Anderson |
| 2011-01-18 | Add support for parsing and encoding ARM's official syntax for the BFI instru... | Bruno Cardoso Lopes |
| 2010-12-14 | Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 | Jim Grosbach |
| 2010-12-13 | Remove the rest of the *_sfp Neon instruction patterns. | Bob Wilson |
| 2010-12-13 | Merge DEBUG statements. | Bill Wendling |
| 2010-12-13 | eliminate the Records global variable, patch by Garrison Venn! | Chris Lattner |
| 2010-12-07 | Remove reference to the CMPz instruction patterns for ARM. | Jim Grosbach |
| 2010-12-03 | I did it wrong. Don't disregard these encodings here. | Bill Wendling |
| 2010-12-03 | Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gpr | Bill Wendling |
| 2010-11-30 | The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e., | Jim Grosbach |
| 2010-11-30 | Tidy up. | Jim Grosbach |
| 2010-11-30 | Delete a few no longer needed references to pseudos. | Jim Grosbach |
| 2010-11-29 | Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw | Jim Grosbach |
