aboutsummaryrefslogtreecommitdiff
path: root/test
AgeCommit message (Collapse)Author
2013-02-14R600: Add lit tests for texture sampling instruction selection.Michel Danzer
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Reapply "s/grep/FileCheck/ in some tests"Andrew Trick
This reverts commit fd1335e982bbf93c5f450ed4fd29f9f787435c85. Use a triple this time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Teach the DataLayout aware constant folder to be much more aggressive towardsNick Lewycky
'and' instructions. This is a pattern that shows up a lot in ubsan binaries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert "s/grep/FileCheck/ in some tests"Andrew Trick
This reverts commit 8b75e6bc35fb3f9c1e788dbd05084c0f4a60a0f3. The FileCheck tests are not equivalent: test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input ; CHECK: jmp init ^ <stdin>:1:2: note: scanning from here .section __TEXT,__text,regular,pure_instructions ^ <stdin>:13:2: note: possible intended match here jmp _init ## TAILCALL ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13temporarily revert the patch due to some conflictsWeiming Zhao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13R600: Add support for 128-bit parametersTom Stellard
NOTE: This is a candidate for the Mesa stable branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13s/grep/FileCheck/ in some testsEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13s/grep/FileCheck/ in some testsEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao
on ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13[ms-inline asm] Fix up test case for non-Darwin platforms.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma
instead of redefining separate instructions for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13[ms-inline-asm] Add support for memory references that have non-immediateChad Rosier
displacements. rdar://12974533 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler
if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Clean up LDV, no functionality change.Manman Ren
Remove dead functions: renameRegister Move private member variables from LDV to Impl Remove ssp/uwtable from testing case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIADavid Peixotto
Fixed bug in tablegen conversion when source pseudo instruction has a different number of arguments than the destination instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer
This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Make jumptables work for -staticReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky
since a caller uses preserved registers across the call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher
assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Finish obviously broken thought.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175035 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13[tsan] disable load widening in ThreadSanitizer modeKostya Serebryany
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.Manman Ren
RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs without emitting them at the end. We fix this by removing LDV from RegisterCoalescer. Also add an assertion to make sure we call emitDebugValues if DBG_VALUEs are removed at runOnMachineFunction. rdar://problem/13183203 Reviewed by Andy & Jakob git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175023 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Remove target-specific info from the testcase for DWARF/pubnames.Krzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12[ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier
This is complicated by backward labels (e.g., 0b can be both a backward label and a binary zero). The current implementation assumes [0-9]b is always a label and thus it's possible for 0b and 1b to not be interpreted correctly for ms-style inline assembly. However, this is relatively simple to fix in the inline assembly (i.e., drop the [bB]). This patch also limits backward labels to [0-9]b, so that only 0b and 1b are ambiguous. Part of rdar://12470373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Allow optionally generating pubnames section in DWARF info. IntroduceKrzysztof Parzyszek
option "generate-dwarf-pubnames" to control it, set to "false" by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174981 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174979 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Fix the lit test added in r174972Paul Redmond
Patch by: Kevin Schoedel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174974 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12PR14562 - Truncation of left shift became undefPaul Redmond
DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32)) into (shl i32 v, 32) into undef. To prevent this, check the shift count against the final result size. Patch by: Kevin Schoedel Reviewed by: Nadav Rotem git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174972 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12[NVPTX] Disable vector registersJustin Holewinski
Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12[asan] fix tests for the new ABIKostya Serebryany
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12Test for string attributes and for attribute group output.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174954 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer
A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad word). radar://13171406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174933 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer
Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12[ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier
Part of rdar://12470373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174926 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11Optimization: bitcast (<1 x ...> insertelement ..., X, ...) to ... ==> ↵Michael Ilseman
bitcast X to ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174905 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek
- variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174904 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11Remove trailing whitespaceMichael Ilseman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174903 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11*fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo
*added file for test cases for i386 intel syntax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11[NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture ↵Justin Holewinski
is not valid in this case, and was causing incorrect optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174896 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11AArch64: generate dwarfdump test rather than include .o in subversionTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174891 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11AArch64: Add basic relocation processing for llvm-dwarfdump.Tim Northover
This allows llvm-dwarfdump to handle the relocations needed, at least for LLVM-produced code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174874 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11AArch64: Undo change to how test was runTim Northover
This broke on Windows, presumably due to interleaving of output streams. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover
This gives a DiagnosticType to all AsmOperands in sight. This replaces all "invalid operand" diagnostics with something more specific. The messages given should still be sufficiently vague that they're not usually actively misleading when LLVM guesses your instruction incorrectly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11FileCheck-ize the tests.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11[tsan/msan] adding thread_safety and uninitialized_checks attributesKostya Serebryany
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174864 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-09LSR IVChain improvement.Andrew Trick
Handle chains in which the same offset is used for both loads and stores to the same array. Fixes rdar://11410078. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174789 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-09Dwarf: do not use line_table_start in at_stmt_list since we do not always emit Manman Ren
line table entries in assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174785 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are theReed Kotler
same so we put in the comment field an indicator when we think we are emitting the 16 bit version. For the direct object emitter, the difference is important as well as for other passes which need an accurate count of program size. There will be other similar putbacks to this for various instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174747 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-18 19:56:25 +0000