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2013-05-08PPCInstrInfo::optimizeCompareInstr should not optimize FP comparesHal Finkel
The floating-point record forms on PPC don't set the condition register bits based on a comparison with zero (like the integer record forms do), but rather based on the exception status bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08This patch fixes two tests marked as XFAIL among the ARM assembler tests.Mihai Popa
The reference encoding is correct, but written in the wrong byte order (these are Thumb tests, while the reference is in ARM byte order). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Fix a bug in codegenprep where it was losing track of values OptimizeMemoryInstNick Lewycky
by switching to a ValueMap. Patch by Andrea DiBiagio! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08DAGCombiner: Simplify inverted bit testsDavid Majnemer
Fold (xor (and x, y), y) -> (and (not x), y) This removes an opportunity for a constant to appear twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181395 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Debug Info: Support DW_TAG_imported_declarationDavid Blaikie
This provides basic functionality for imported declarations. For subprograms and types some amount of lazy construction is supported (so the definition of a function can proceed the using declaration), but it still doesn't handle declared-but-not-defined functions (since we don't generally emit function declarations). Variable support is really rudimentary at the moment - simply looking up the existing definition with no support for out of order (declaration, imported_module, then definition). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07LoopVectorizer: Improve reduction variable identificationArnold Schwaighofer
The two nested loops were confusing and also conservative in identifying reduction variables. This patch replaces them by a worklist based approach. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07Fix a bug in the MC asm parser evaluating expressions. It was treating:Kevin Enderby
A = 9 B = 3 * A - 2 * A + 1 as B = 3 * A - (2 * A + 1) rdar://13816516 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07Debug Info: Fix for break due to r181271David Blaikie
Apparently we didn't keep an association of Compile Unit metadata nodes to DIEs so looking up that parental context failed & thus caused no DW_TAG_imported_modules to be emitted at the CU scope. Fix this by adding the mapping & sure up the test case to verify this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07Reverting r181331.Jyotsna Verma
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181331 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-07LoopVectorize: getConsecutiveVector must respect signed arithmeticArnold Schwaighofer
We were passing an i32 to ConstantInt::get where an i64 was needed and we must also pass the sign if we pass negatives numbers. The start index passed to getConsecutiveVector must also be signed. Should fix PR15882. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06DebugInfo: Support imported modules in lexical blocksDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06InstCombine: (X ^ signbit) + C -> X + (signbit ^ C)David Majnemer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Reduce attributes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Split Alignment out of the Section Characteristics.Rafael Espindola
The alignment is just a byte in the middle of Characteristics, not an independent flag. Making it an independent field in the yaml representation makes it more yamlio friendly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Test results verified using FileCheck rather than grep | countJean-Luc Duprat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181234 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Rotate multi-exit loops even if the latch was simplified.Andrew Trick
Test case by Michele Scandale! Fixes PR10293: Load not hoisted out of loop with multiple exits. There are few regressions with this patch, now tracked by rdar:13817079, and a roughly equal number of improvements. The regressions are almost certainly back luck because LoopRotate has very little idea of whether rotation is profitable. Doing better requires a more comprehensive solution. This checkin is a quick fix that lacks generality (PR10293 has a counter-example). But it trivially fixes the case in PR10293 without interfering with other cases, and it does satify the criteria that LoopRotate is a loop canonicalization pass that should avoid heuristics and special cases. I can think of two approaches that would probably be better in the long run. Ultimately they may both make sense. (1) LoopRotate should check that the current header would make a good loop guard, and that the loop does not already has a sufficient guard. The artifical SimplifiedLoopLatch check would be unnecessary, and the design would be more general and canonical. Two difficulties: - We need a strong guarantee that we won't endlessly rotate, so the analysis would need to be precise in order to avoid the SimplifiedLoopLatch precondition. - Analysis like this are usually based on SCEV, which we don't want to rely on. (2) Rotate on-demand in late loop passes. This could even be done by shoving the loop back on the queue after the optimization that needs it. This could work well when we find LICM opportunities in multi-branch loops. This requires some work, and it doesn't really solve the problem of SCEV wanting a loop guard before the analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Emit config values in register / value pairsTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Stop emitting the instruction type byte before each instructionTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06R600: Emit ISA for CALL_FS_* instructionsTom Stellard
Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06[SystemZ] Update non-pic DWARF encodingsUlrich Weigand
As pointed out by Rafael Espindola, we should match the DWARF encodings produced by GCC in both pic and non-pic modes. This was not the case for the non-pic case. This patch changes all DWARF encodings to DW_EH_PE_absptr for the non-pic case, just like GCC does. The test case is updated to check for both variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06PowerPC: Fix unimplemented relocation on ppc64Adhemerval Zanella
This patch handles the R_PPC64_REL64 relocation type for powerpc64 for mcjit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Fix add4.ll test cmdline so that it passesJean-Luc Duprat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Provide InstCombines for the following 3 cases:Jean-Luc Duprat
A * (1 - (uitofp i1 C)) -> select C, 0, A B * (uitofp i1 C) -> select C, B, 0 select C, 0, A + select C, B, 0 -> select C, B, A These come up in code that has been hand-optimized from a select to a linear blend, on platforms where that may have mattered. We want to undo such changes with the following transform: A*(1 - uitofp i1 C) + B*(uitofp i1 C) -> select C, A, B git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181216 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06AArch64: use MCJIT by default and enable related tests.Tim Northover
This just enables some testing I'd missed after implementing MCJIT support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06[SystemZ] Set up JIT/MCJIT test casesUlrich Weigand
This patch adds the necessary configuration bits and #ifdef's to set up the JIT/MCJIT test cases for SystemZ. Like other recent targets, we do fully support MCJIT, but do not support the old JIT at all. Set up the lit config files accordingly, and disable old-JIT unit tests. Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06[SystemZ] Add MC test casesUlrich Weigand
This adds all MC tests for the SystemZ target. Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181206 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06[SystemZ] Add DebugInfo test casesUlrich Weigand
This adds all DebugInfo tests for the SystemZ target. This version of the patch incorporates feedback from reviews by Eric Christopher and Rafael Espindola. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06[SystemZ] Add CodeGen test casesUlrich Weigand
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Free the exception object. Should fix the vg bots.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181195 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Fix slightly too aggressive conact_vector optimization.Michael Kuperstein
(Would sometimes optimize away conacts used to extend a vector with undef values) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Add a testcase that checks that we generate functions with frameBill Wendling
pointers or not depending upon the function attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06XFAIL for cygwin.Rafael Espindola
Looks like symbol resolution is not working on cygwin, the test fails because __gxx_personality_v0 is not found. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Revert r164763 because it introduces new shuffles.Nadav Rotem
Thanks Nick Lewycky for pointing this out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181177 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Fix unchecked uses of DominatorTree in MemoryDependenceAnalysis.Matt Arsenault
Use unknown results for places where it would be needed git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06Fix const merging when an alias of a const is llvm.used.Rafael Espindola
We used to disable constant merging not only if a constant is llvm.used, but also if an alias of a constant is llvm.used. This change fixes that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05This should also fail on ARM.Rafael Espindola
We currently have no way to register new eh frames on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05Fix XFAIL line.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05XFAIL this on ppc64.Rafael Espindola
It looks like eh uses an unimplemented relocation on pp64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05Add EH support to the MCJIT.Rafael Espindola
This gets exception handling working on ELF and Macho (x86-64 at least). Other than the EH frame registration, this patch also implements support for GOT relocations which are used to locate the personality function on MachO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181167 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05Test case for r181160 and r181161. rdar://13782395Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Add LDAPB instructions.Richard Osborne
With the change the disassembler now supports the XCore ISA in its entirety. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Add BLRB instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05For ARM backend, fixed "byval" attribute support.Stepan Dyatkovskiy
Now even the small structures could be passed within byval (small enough to be stored in GPRs). In regression tests next function prototypes are checked: PR15293: %artz = type { i32 } define void @foo(%artz* byval %s) define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) foo: "s" stored in R0 foo2: "s" stored in R0, "s2" stored in R2. Next AAPCS rules are checked: 5.5 Parameters Passing, C.4 and C.5, "ParamSize" is parameter size in 32bit words: -- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4. Parameter should be sent to the stack; NCRN := R4. -- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4. Parameter stored in GPRs; NCRN += ParamSize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05Remove a recently redundant transform from X86ISelLowering.David Majnemer
X86ISelLowering has support to treat: (icmp ne (and (xor %flags, -1), (shl 1, flag)), 0) as if it were actually: (icmp eq (and %flags, (shl 1, flag)), 0) However, r179386 has code at the InstCombine level to handle this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05LoopVectorize: Add support for floating point min/max reductionsArnold Schwaighofer
Add support for min/max reductions when "no-nans-float-math" is enabled. This allows us to assume we have ordered floating point math and treat ordered and unordered predicates equally. radar://13723044 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05LoopVectorize: We don't need an identity element for min/max reductionsArnold Schwaighofer
We can just use the initial element that feeds the reduction. max(max(x, y), z) == max(max(x,y), max(x,z)) radar://13723044 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04AArch64: enable MCJIT and tests now that everything passes.Tim Northover
This removes dire warnings about AArch64 being unsupported and enables the tests when appropriate on this platform. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04AArch64: support literal pool access in large memory model.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181120 91177308-0d34-0410-b5e6-96231b3b80d8
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