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2013-01-30PPC QPX requires a 32-byte aligned stackHal Finkel
On systems which support the QPX vector instructions, the stack must be 32-byte aligned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173993 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Forgot the test case before.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Add definitions for the PPC a2q core marked as having QPX availableHal Finkel
This is the first commit of a large series which will add support for the QPX vector instruction set to the PowerPC backend. This instruction set is used on the IBM Blue Gene/Q supercomputers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Linker: correctly link in dbg.declareManman Ren
Given source IR: call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !14), !dbg !15 we used to generate call void @llvm.dbg.declare(metadata !27, metadata !28), !dbg !29 !27 = metadata !{null} With this patch, we will correctly generate call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !27), !dbg !28 Looking up %argc.addr in ValueMap will return null, since %argc.addr is already correctly set up, we can use identity mapping. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Add a special ARM trap encoding for NaCl.Eli Bendersky
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Add missing header and test cases for r173939.Logan Chien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173941 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30InstCombine: canonicalize sext-and --> selectNadav Rotem
sext-not-and --> select. Patch by Muhammad Tauqir Ahmad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30build: add --with-python optionSaleem Abdulrasool
This adds a new --with-python option to allow configuration of the python binary for building. If not specified, $PATH will be searched for common python binary names (python, python2, python3). If specified, and the path is not executable, it will attempt to search $PATH. Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> Reviewed-by: Eric Christopher <echristo@gmail.com>, Daniel Dunbar <daniel@zuster.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173890 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30This patch implements runtime ARM specificJack Carter
setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30This patch implements runtime Mips specificJack Carter
setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30This patch reworks how llvm targets set Jack Carter
and update ELF header e_flags. Currently gathering information such as symbol, section and data is done by collecting it in an MCAssembler object. From MCAssembler and MCAsmLayout objects ELFObjectWriter::WriteObject() forms and streams out the ELF object file. This patch just adds a few members to the MCAssember class to store and access the e_flag settings. It allows for runtime additions to the e_flag by assembler directives. The standalone assembler can get to MCAssembler from getParser().getStreamer().getAssembler(). This patch is the generic infrastructure and will be followed by patches for ARM and Mips for their target specific use. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30[mips] Test case for r173862.Akira Hatanaka
Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173863 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Adding simple cast cost to ARMRenato Golin
Changing ARMBaseTargetMachine to return ARMTargetLowering intead of the generic one (similar to x86 code). Tests showing which instructions were added to cast when necessary or cost zero when not. Downcast to 16 bits are not lowered in NEON, so costs are not there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173849 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29[MC][COFF] Delay handling symbol aliases when writingMichael J. Spencer
Fixes PR14447 and PR9034. Patch by Nico Rieck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173839 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29LoopVectorize: convert TinyTripCountVectorThreshold constantPekka Jaaskelainen
to a command line switch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173837 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Support artificial parameters in function types.David Blaikie
Provides the functionality for Clang change r172911 - I just had this still lying around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Fix 64-bit atomic operations in Thumb mode.Tim Northover
The ARM and Thumb variants of LDREXD and STREXD have different constraints and take different operands. Previously the code expanding atomic operations didn't take this into account and asserted in Thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Convert getAttributes() to return an AttributeSetNode.Bill Wendling
The AttributeSetNode contains all of the attributes. This removes one (hopefully last) use of the Attribute class as a container of multiple attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Add support for source and line information to IntelJITEventListener for ↵Andrew Kaylor
object emitted by MCJIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173712 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28This patch addresses bug 15031.Bill Schmidt
The common code in the post-RA scheduler to break anti-dependencies on the critical path contained a flaw. In the reported case, an anti-dependency between the overlapping registers %X4 and %R4 exists: %X29<def> = OR8 %X4, %X4 %R4<def>, %X3<def,dead,tied3> = LBZU 1, %X3<kill,tied1> The unpatched code breaks the dependency by replacing %R4 and its uses with %R3, the first register on the available list. However, %R3 and %X3 overlap, so this creates two overlapping definitions on the same instruction. The fix is straightforward, preventing selection of a register that overlaps any other defined register on the same instruction. The test case is reduced from the bug report, and verifies that we no longer produce "lbzu 3, 1(3)" when breaking this anti-dependency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173706 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28[msan] Mostly disable msan-handle-icmp-exact.Evgeniy Stepanov
It is way too slow. Change the default option value to 0. Always do exact shadow propagation for unsigned ICmp with constants, it is cheap (under 1% cpu time) and required for correctness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper
independent 256-bit lanes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2rus instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 1r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 0r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27When the legalizer is splitting vector shifts, the result may not have the ↵Benjamin Kramer
right shift amount type. Fix that by adding a cast to the shift expander. This came up with vector shifts on sse-less X86 CPUs. <2 x i64> = shl <2 x i64> <2 x i64> -> i64,i64 = shl i64 i64; shl i64 i64 -> i32,i32,i32,i32 = shl_parts i32 i32 i64; shl_parts i32 i32 i64 Now we cast the last two i64s to the right type. Fixes the crash in PR14668. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173615 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27Re-revert r173342, without losing the compile time improvements, flatChandler Carruth
out bug fixes, or functionality preserving refactorings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26PR14566: Debug Info: Removing top level lexical blocksDavid Blaikie
This adds support for LLVM to accept metadata that doesn't include a top level lexical block in a function. Specifically LLVM couldn't handle this when there were file changes relating to these blocks. I've updated a few test cases to ensure other functionality (such as inlining) isn't affected by this change, but haven't pervasively updated all the test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer
This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26FileCheckize and merge some tests.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26Add DIContext::getLineInfoForAddressRange() function and test. This ↵Andrew Kaylor
function allows a caller to obtain a table of line information for a function using the function's address and size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25llvm/test/CMakeLists.txt: Add a dependency to llvm-rtdyld in check-llvm.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Initial implementation of PPCTargetTransformInfoHal Finkel
This provides a place to add customized operation cost information and control some other target-specific IR-level transformations. The only non-trivial logic in this checkin assigns a higher cost to unaligned loads and stores (covered by the included test case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add support for applying in-memory relocations to the .debug_line section ↵Andrew Kaylor
and, in the case of ELF files, using symbol addresses when available for relocations to the .debug_info section. Also extending the llvm-rtdyld tool to add the ability to dump line number information for testing purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173517 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25XFAIL close-stderr on win32Reid Kleckner
The test runner does not rewrite instances of /dev/null inside the quoted sh command. /dev/null does not exist, so opt will fail to open it, and return a non-zero exit code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173509 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Set the +x bit on two batch scriptsReid Kleckner
Cygwin git-svn will faithfully forward the svn properties all the way down to the NTFS executable permission. Without the +x bit, tests using these scripts fail with "Access Denied". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25FileCheck-ify some grep testsReid Kleckner
These tests in particular try to use escaped square brackets as an argument to grep, which is failing for me with native win32 python. It appears the backslash is being lost near the CreateProcess*() call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky
(defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add back a RUN line removed by mistake by a previous commitEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173502 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l4r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,Eli Bendersky
use them in tests that run llvm-dwarfdump. This is in order to make tests as specific as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Improve the !add TableGen test case.Hal Finkel
Suggested by Sean Silva. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173481 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add command-line flags for DWARF dumping.Eli Bendersky
Flags for dumping specific DWARF sections added in lib/DebugInfo and llvm-dwarfdump. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l5r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25[msan] Implement exact shadow propagation for relational ICmp.Evgeniy Stepanov
Only for integers, pointers, and vectors of those. No floats. Instrumentation seems very heavy, and may need to be replaced with some approximation in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173452 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add an addition operator to TableGenHal Finkel
This adds an !add(a, b) operator to tablegen; this will be used to cleanup the PPC register definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Fixed the condition codes for the atomic64 min/umin code generation on ARM. ↵Silviu Baranga
If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
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