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2013-01-17Optimization for the following SIGN_EXTEND pairs:Elena Demikhovsky
v8i8 -> v8i64, v8i8 -> v8i32, v4i8 -> v4i64, v4i16 -> v4i64 for AVX and AVX2. Bug 14865. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Fix the assembly and dissassembly of DW_FORM_sec_offset. Found this byEric Christopher
changing both the string of the dwo_name to be correct and the type of the statement list. Testcases all around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Add the DW_AT_GNU_addr_base for the skeleton cu. Add support forEric Christopher
emitting the dwarf32 version of DW_FORM_sec_offset and correct disassembler support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172698 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17This is a resubmittal. For some reason it broke the bots yesterdayJack Carter
but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16[IR] Add 'Append' and 'AppendUnique' module flag behaviors.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Added test for r172599 which fixes bugzilla://14584,rdar://11744105.Michael Gottesman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Make this test X86 only.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172652 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Move this to X86.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172651 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Add testcase missed yesterday from Paul Robinson.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172646 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16[Linker] Change module flag linking to be more extensible.Daniel Dunbar
- Instead of computing a bunch of buckets of different flag types, just do an incremental link resolving conflicts as they arise. - This also has the advantage of making the link result deterministic and not dependent on map iteration order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16We want the dwarf AT_producer for assembly source files to match clang'sKevin Enderby
AT_producer. Which includes clang's version information so we can tell which version of the compiler was used. This is the first of two steps to allow us to do that. This is the llvm-mc change to provide a method to set the AT_producer string. The second step, coming soon to a clang near you, will have the clang driver pass the value of getClangFullVersion() via an flag when invoking the integrated assembler on assembly source files. rdar://12955296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172630 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Introduce llvm::sys::getProcessTriple() function.Peter Collingbourne
In r143502, we renamed getHostTriple() to getDefaultTargetTriple() as part of work to allow the user to supply a different default target triple at configure time. This change also affected the JIT. However, it is inappropriate to use the default target triple in the JIT in most circumstances because this will not necessarily match the current architecture used by the process, leading to illegal instruction and other such errors at run time. Introduce the getProcessTriple() function for use in the JIT and its clients, and cause the JIT to use it. On architectures with a single bitness, the host and process triples are identical. On other architectures, the host triple represents the architecture of the host CPU, while the process triple represents the architecture used by the host CPU to interpret machine code within the current process. For example, when executing 32-bit code on a 64-bit Linux machine, the host triple may be 'x86_64-unknown-linux-gnu', while the process triple may be 'i386-unknown-linux-gnu'. This fixes JIT for the 32-on-64-bit (and vice versa) build on non-Apple platforms. Differential Revision: http://llvm-reviews.chandlerc.com/D254 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172627 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Move test that depends on the x86 target into a target-specific directory.Benjamin Kramer
Should fix the arm buildbot (which only builds the arm target). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16ASan: wrap mapping scale and offset in a struct and make it a member of ASan ↵Alexey Samsonov
passes. Add test for non-default mapping scale and offset. No functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Remove triple from this test, it makes it fail when X86 TTI is missing.Benjamin Kramer
Without a triple opt falls back to NoTTI which comes closer to LSR's pre-TTI behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16reverting 172579Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Akira,Jack Carter
Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15Split address information for DWARF5 split dwarf proposal. This involvesEric Christopher
using the DW_FORM_GNU_addr_index and a separate .debug_addr section which stays in the executable and is fully linked. Sneak in two other small changes: a) Print out the debug_str_offsets.dwo section. b) Change form we're expecting the entries in the debug_str_offsets.dwo section to take from ULEB128 to U32. Add tests for all of this in the fission-cu.ll test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172578 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15Teach InstCombine to optimize extract of a value from a vector add operation ↵Nadav Rotem
with a constant zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-151. Hoist minus sign as high as possible in an attempt to revealShuxin Yang
some optimization opportunities (in the enclosing supper-expressions). rule 1. (-0.0 - X ) * Y => -0.0 - (X * Y) if expression "-0.0 - X" has only one reference. rule 2. (0.0 - X ) * Y => -0.0 - (X * Y) if expression "0.0 - X" has only one reference, and the instruction is marked "noSignedZero". 2. Eliminate negation (The compiler was already able to handle these opt if the 0.0s are replaced with -0.0.) rule 3: (0.0 - X) * (0.0 - Y) => X * Y rule 4: (0.0 - X) * C => X * -C if the expr is flagged "noSignedZero". 3. Rule 5: (X*Y) * X => (X*X) * Y if X!=Y and the expression is flagged with "UnsafeAlgebra". The purpose of this transformation is two-fold: a) to form a power expression (of X). b) potentially shorten the critical path: After transformation, the latency of the instruction Y is amortized by the expression of X*X, and therefore Y is in a "less critical" position compared to what it was before the transformation. 4. Remove the InstCombine code about simplifiying "X * select". The reasons are following: a) The "select" is somewhat architecture-dependent, therefore the higher level optimizers are not able to precisely predict if the simplification really yields any performance improvement or not. b) The "select" operator is bit complicate, and tends to obscure optimization opportunities. It is btter to keep it as low as possible in expr tree, and let CodeGen to tackle the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172551 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15[IR] Add verification for module flags with the "require" behavior.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15[msan] Temporarily remove ICmpEQ tests.Evgeniy Stepanov
They are failing on the bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172540 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15[msan] Fix handling of equality comparison of pointer vectors.Evgeniy Stepanov
Also improve test coveration of the handling of relational comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15Pattern-matched variables in post-inc-icmpzero.llRenato Golin
Test was failing for clang-native-arm-cortex-a9 build-bot configuration. The reason for the failure was the test was using hardcoded names. The attached patch fixes this failure by replacing the hard-coded variables names with pattern-matched variable names. Patch by Manish Verma, ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172534 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15[IR] Add verifier support for llvm.module.flags.Daniel Dunbar
- Also, update the LangRef documentation on module flags to match the implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15This patch fixes a Mips specific bug where Jack Carter
we need to generate a N64 compound relocation R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE. The bug was exposed by the SingleSourcetest case DuffsDevice.c. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14This change is to implement following rules under the condition C_A and/or C_RShuxin Yang
--------------------------------------------------------------------------- C_A: reassociation is allowed C_R: reciprocal of a constant C is appropriate, which means - 1/C is exact, or - reciprocal is allowed and 1/C is neither a special value nor a denormal. ----------------------------------------------------------------------------- rule1: (X/C1) / C2 => X / (C2*C1) (if C_A) => X * (1/(C2*C1)) (if C_A && C_R) rule 2: X*C1 / C2 => X * (C1/C2) if C_A rule 3: (X/Y)/Z = > X/(Y*Z) (if C_A && at least one of Y and Z is symbolic value) rule 4: Z/(X/Y) = > (Z*Y)/X (similar to rule3) rule 5: C1/(X*C2) => (C1/C2) / X (if C_A) rule 6: C1/(X/C2) => (C1*C2) / X (if C_A) rule 7: C1/(C2/X) => (C1/C2) * X (if C_A) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172488 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14[ms-inline asm] Extend support for parsing Intel bracketed memory operands thatChad Rosier
have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14This patch addresses an incorrect transformation in the DAG combiner.Bill Schmidt
The included test case is derived from one of the GCC compatibility tests. The problem arises after the selection DAG has been converted to type-legalized form. The combiner first sees a 64-bit load that can be converted into a pre-increment form. The original load feeds into a SRL that isolates the upper 32 bits of the loaded doubleword. This looks like an opportunity for DAGCombiner::ReduceLoadWidth() to replace the 64-bit load with a 32-bit load. However, this transformation is not valid, as the replacement load is not a pre-increment load. The pre-increment load produces an extra result, which feeds a subsequent add instruction. The replacement load only has one result value, and this value is propagated to all uses of the pre- increment load, including the add. Because the add is looking for the second result value as its operand, it ends up attempting to add a constant to a token chain, resulting in a crash. So the patch simply disables this transformation for any load with more than two result values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14SCEVExpander fix. RAUW needs to update the InsertedExpressions cache.Andrew Trick
Note that this bug is only exposed because LTO fails to use TTI. Fixes self-LTO of clang. rdar://13007381. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172462 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13Added bugzilla PR number to test case.Michael Gottesman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13Fixed an infinite loop in the block escape in analysis in ObjCARC caused by ↵Michael Gottesman
2x blocks each assigned a value via a phi-node causing each to depend on the other. A test case is provided as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172368 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13X86: Add patterns for X86ISD::VSEXT in registers.Benjamin Kramer
Those can occur when something between the sextload and the store is on the same chain and blocks isel. Fixes PR14887. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13Fix PR14547. Handle induction variables of small sizes smaller than i32 (i8 ↵Nadav Rotem
and i16). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12When lowering an inreg sext first shift left, then right arithmetically.Benjamin Kramer
Shifting right two times will only yield zero. Should fix SingleSource/UnitTests/SignlessTypes/factor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12Fixed bug in ObjCARC where we were changing a call from objc_autoreleaseRV ↵Michael Gottesman
=> objc_autorelease but were not updating the InstructionClass to IC_Autorelease. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12Fixed a bug where we were tail calling objc_autorelease causing an object to ↵Michael Gottesman
not be placed into an autorelease pool. The reason that this occurs is that tail calling objc_autorelease eventually tail calls -[NSObject autorelease] which supports fast autorelease. This can cause us to violate the semantic gaurantees of __autoreleasing variables that assignment to an __autoreleasing variables always yields an object that is placed into the innermost autorelease pool. The fix included in this patch works by: 1. In the peephole optimization function OptimizeIndividualFunctions, always remove tail call from objc_autorelease. 2. Whenever we convert to/from an objc_autorelease, set/unset the tail call keyword as appropriate. *NOTE* I also handled the case where objc_autorelease is converted in OptimizeReturns to an autoreleaseRV which still violates the ARC semantics. I will be removing that in a later patch and I wanted to make sure that the tree is in a consistent state vis-a-vis ARC always. Additionally some test cases are provided and all tests that have tail call marked objc_autorelease keywords have been modified so that tail call has been removed. *NOTE* One test fails due to a separate bug that I am going to commit soon. Thus I marked the check line TMP: instead of CHECK: so make check does not fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172287 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12This patch tackles the problem of parsing Mips Jack Carter
register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11PPC: Implement efficient lowering of sign_extend_inreg.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11Update patch for the pad short functions pass for Intel Atom (only).Preston Gurd
Adds a check for -Oz, changes the code to not re-visit BBs, and skips over DBG_VALUE instrs. Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11ARM Cost Model: Modify the target independent cost model to askNadav Rotem
the target if it supports the different CAST types. We didn't do this on X86 because of the different register sizes and types, but on ARM this makes sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11For inline asm:Eric Christopher
- recognize string "{memory}" in the MI generation - mark as mayload/maystore when there's a memory clobber constraint. PR14859. Patch by Krzysztof Parzyszek git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11Simplify writing floating types to assembly.Tim Northover
This removes previous special cases for each floating-point type in favour of a shared codepath. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11ARM Cost Model: We need to detect the max bitwidth of types in the loop in ↵Nadav Rotem
order to select the max vectorization factor. We don't have a detailed analysis on which values are vectorized and which stay scalars in the vectorized loop so we use another method. We look at reduction variables, loads and stores, which are the only ways to get information in and out of loop iterations. If the data types are extended and truncated then the cost model will catch the cost of the vector zext/sext/trunc operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172178 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11Converted test dont-tce-tail-marked-call.ll to use FileCheck.Michael Gottesman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11This commit is a 4x squash commit consisting of 4x functions converted to ↵Michael Gottesman
use FileCheck instead of grep. Messages: Converted test case trivial_codegen_tailcall.ll to use FileCheck. Converted test return_constant.ll to use FileCheck instead of grep. Converted test reorder_load.ll to use FileCheck instead of grep. Converted test intervening-inst.ll to use FileCheck instead of grep. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10PR14904: Segmentation fault running pass 'Recognize loop idioms'Shuxin Yang
The root cause is mistakenly taking for granted that "dyn_cast<Instruction>(a-Value)" return a non-NULL instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10CastInst::castIsValid should return true if the dest type is the same asEvan Cheng
Value's current type. The casting is trivial even for aggregate type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10llvm/test/CodeGen/X86/ms-inline-asm.ll: Fixup; Globals doesn't have leading ↵NAKAMURA Takumi
underscore in symbol on linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172139 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10[llvm-objdump] Emit addresses with the correct number of leading 0's.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172130 91177308-0d34-0410-b5e6-96231b3b80d8
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