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2013-01-24The next phase of Mips16 hard float implementation.Reed Kotler
Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23ConstantFolding: Evaluate GEP indices in the index type.Benjamin Kramer
This fixes some edge cases that we would get wrong with uint64_ts. PR14986. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173289 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Add instruction encodings / disassembly support for l6r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Revert "InstCombine: Clean up weird code that talks about a modulus that's ↵Benjamin Kramer
long gone." This causes crashes during the build of compiler-rt during selfhost. Add a testcase for coverage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Add the heuristic to differentiate SSPStrong from SSPRequired.Bill Wendling
The requirements of the strong heuristic are: * A Protector is required for functions which contain an array, regardless of type or length. * A Protector is required for functions which contain a structure/union which contains an array, regardless of type or length. Note, there is no limit to the depth of nesting. * A protector is required when the address of a local variable (i.e., stack based variable) is exposed. (E.g., such as through a local whose address is taken as part of the RHS of an assignment or a local whose address is taken as part of a function argument.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Add the IR attribute 'sspstrong'.Bill Wendling
SSPStrong applies a heuristic to insert stack protectors in these situations: * A Protector is required for functions which contain an array, regardless of type or length. * A Protector is required for functions which contain a structure/union which contains an array, regardless of type or length. Note, there is no limit to the depth of nesting. * A protector is required when the address of a local variable (i.e., stack based variable) is exposed. (E.g., such as through a local whose address is taken as part of the RHS of an assignment or a local whose address is taken as part of a function argument.) This patch implements the SSPString attribute to be equivalent to SSPRequired. This will change in a subsequent patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Add support for reverse pointer induction variables. These are loops that ↵Nadav Rotem
contain pointers that count backwards. For example, this is the hot loop in BZIP: do { m = *--p; *p = ( ... ); } while (--n); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao
- Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Add a warning when there is a macro defintion that has named parameters butKevin Enderby
the body does not use them and it appears the body has positional parameters. This can cause unexpected results as in the added test case. As the darwin version of gas(1) which only supported positional parameters, happened to ignore the named parameters. Now that we want to support both styles of macros we issue a warning in this specific case. rdar://12861644 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22[mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173197 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Have the integrated assembler give an error if $1 is used as an identifier inKevin Enderby
an expression. Currently this bug causes the line to be ignored in a release build and an assert in a debug build. rdar://13062484 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173195 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Add forgotten test case for the x32 commitEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer
rip-rel relocations will be off by one byte. PR15040. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ↵Dmitri Gribenko
ModuleID This is done to avoid odd test failures, like the one fixed in r171243. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173163 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22[msan] Do not insert check on volatile store.Evgeniy Stepanov
Volatile bitfields can cause valid stores of uninitialized bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173153 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22This test is only supposed to test that the objc-arc alias analysisMichael Gottesman
allows for gvn to perform certain optimizations. Thus the runline should only contain -objc-arc-aa, not the full -objc-arc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22[MC/Mach-O] Load commands are supposed to 8-byte aligned on 64-bit.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Remove target triple from an LSR test.Andrew Trick
Manish already fixed this test to work with NoTTI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173110 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Transform (sub 0, (zext bool to A)) to (sext bool to A) andPaul Redmond
(sub 0, (sext bool to A)) to (zext bool to A). Patch by Muhammad Ahmad Reviewed by Duncan Sands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173093 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Add instruction encodings / disassembly support for u6 / lu6 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Add instruction encoding / disassembly support for ru6 / lru6 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support for l3r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support 3r instructions.Richard Osborne
It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20llvm/test/CodeGen/X86/win_ftol2.ll: Add -cpu=generic to appease valgrind.NAKAMURA Takumi
On valgrind the processor is reported; Host CPU: athlon-fx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172983 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Revert 172708.Nadav Rotem
The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends. This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical. Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20LoopVectorizer: Implement a new heuristics for selecting the unroll factor.Nadav Rotem
We ignore the cpu frontend and focus on pipeline utilization. We do this because we don't have a good way to estimate the loop body size at the IR level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172964 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Change the cpu type in the test.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172963 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20llvm/test/Other/close-stderr.ll: Mark this as XFAIL:valgrind. We got 127 ↵NAKAMURA Takumi
instead of 1 here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20The last of PR14471 - emission of constant floatsDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172941 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19Fix a latent bug exposed by recent static member debug info changes.David Blaikie
We weren't encoding boolean constants correctly due to modeling boolean as a signed type & then sign extending an i1 up to a byte & getting 255. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172926 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19LoopVectorizer: Emit memory checks into their own basic block.Benjamin Kramer
This separates the check for "too few elements to run the vector loop" from the "memory overlap" check, giving a lot nicer code and allowing to skip the memory checks when we're not going to execute the vector code anyways. We still leave the decision of whether to emit the memory checks as branches or setccs, but it seems to be doing a good job. If ugly code pops up we may want to emit them as separate blocks too. Small speedup on MultiSource/Benchmarks/MallocBench/espresso. Most of this is legwork to allow multiple bypass blocks while updating PHIs, dominators and loop info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172902 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19On Sandybridge split unaligned 256bit stores into two xmm-sized stores. Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172894 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19Remove some register allocation order dependencies.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172874 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18On Sandybridge loading unaligned 256bits using two XMM loads (vmovups and ↵Nadav Rotem
vinsertf128) is faster than using a single vmovups instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18Split out DW_OP_addr for the split debug info DWARF5 proposal.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172857 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18This is a resubmittal. For some reason it broke the bots yesterdayJack Carter
but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Support for Mips register information sections. Mips ELF object files have a section that is dedicated to register use info. Some of this information such as the assumed Global Pointer value is used by the linker in relocation resolution. The register info file is .reginfo in o32 and .MIPS.options in 64 and n32 abi files. This patch contains the changes needed to create the sections, but leaves the actual register accounting for a future patch. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18This is a resubmittal. For some reason it broke the bots yesterdayJack Carter
but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18[MC/Mach-O] Implement integrated assembler support for linker options.Daniel Dunbar
- Also, fixup syntax errors in LangRef and missing newline in the MCAsmStreamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172837 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18llvm/test/CodeGen/X86/Atomics-64.ll: Tweak for 2nd RUN not to overwrite %t. ↵NAKAMURA Takumi
It sometimes causes spurious failure on lit win32. Feel free to prune or suppress each output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18[MC/Mach-O] Add support for linker options in Mach-O files.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18[MC/Mach-O] Add AsmParser support for .linker_option directive.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Reverting r171325 & r172363. This was causing a mis-compile on the ↵Bill Wendling
self-hosted LTO build bots. Okay, here's how to reproduce the problem: 1) Build a Release (or Release+Asserts) version of clang in the normal way. 2) Using the clang & clang++ binaries from (1), build a Release (or Release+Asserts) version of the same sources, but this time enable LTO --- specify the `-flto' flag on the command line. 3) Run the ARC migrator tests: $ arcmt-test --args -triple x86_64-apple-darwin10 -fsyntax-only -x objective-c++ ./src/tools/clang/test/ARCMT/cxx-rewrite.mm You'll see that the output isn't correct (the whitespace is off). The mis-compile is in the function `RewriteBuffer::RemoveText' in the clang/lib/Rewrite/Core/Rewriter.cpp file. When that function and RewriteRope.cpp are compiled with LTO and the `arcmt-test' executable is regenerated, you'll see the error. When those files are not LTO'ed, then the output of the `arcmt-test' is fine. It is *really* hard to get a testcase out of this. I'll file a PR with what I have currently. --- Reverse-merging r172363 into '.': U include/llvm/Analysis/MemoryBuiltins.h U lib/Analysis/MemoryBuiltins.cpp --- Reverse-merging r171325 into '.': U test/Transforms/InstCombine/objsize.ll G include/llvm/Analysis/MemoryBuiltins.h G lib/Analysis/MemoryBuiltins.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Restore reverted test case, this time with REQUIRES: assertsBill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Remove bad test caseBill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17This patch fixes PR13626 by providing i128 support in the returnBill Schmidt
calling convention. 128-bit integers are now properly returned in GPR3 and GPR4 on PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Add indexed load/store instructions for offset validation check.Jyotsna Verma
This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17This patch fixes the PPC calling convention to handle returns ofBill Schmidt
_Complex float and _Complex long double, by simply increasing the number of floating point registers available for return values. The test case verifies that the correct registers are loaded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172733 91177308-0d34-0410-b5e6-96231b3b80d8
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