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2013-03-07SimplifyCFG fix for volatile load/store.Andrew Trick
Fixes rdar:13349374. Volatile loads and stores need to be preserved even if the language standard says they are undefined. "volatile" in this context means "get out of the way compiler, let my platform handle it". Additionally, this is the only way I know of with llvm to write to the first page (when hardware allows) without dropping to assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176599 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-07Fix two remaining issue after fixing PR15355 when CMOV is not availableMichael Liao
- Phi nodes should be replaced/updated after lowering CMOV into branch because 'mainMBB' updating operand in Phi node is changed. - Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as we will reuse the EFLAGS generated before the 1st lowered CMOV, which won't clobber EFLAGS. However, we need explicitly specify that. - '-attr=-cmov' test case are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06[mips] Custom-legalize BR_JT.Akira Hatanaka
In N64-static, GOT address is needed to compute the branch address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06Memory Dependence Analysis (not mem-dep test) take advantage of ↵Shuxin Yang
"invariant.load" metadata. The "invariant.load" metadata indicates the memory unit being accessed is immutable. A load annotated with this metadata can be moved across any store. As I am not sure if it is legal to move such loads across barrier/fence, this change dose not allow such transformation. rdar://11311484 Thank Arnold for code review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06InstCombine: Don't shrink allocas when combining with a bitcast.Jim Grosbach
When considering folding a bitcast of an alloca into the alloca itself, make sure we don't shrink the amount of memory being allocated, or things rapidly go sideways. rdar://13324424 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176547 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06[mips] Add a line which checks function name. Rename file.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176543 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06Fix PR15355Michael Liao
- Clear 'mayStore' flag when loading from the atomic variable before the spin loop - Clear kill flag from one use to multiple use in registers forming the address to that atomic variable - don't use a physical register as live-in register in BB (neither entry nor landing pad.) by copying it into virtual register (patch by Cameron Zwarich) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176538 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05[mips] Remove android calling convention.Akira Hatanaka
This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05[mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 getsAkira Hatanaka
returned in registers $2 and $4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctlyAkira Hatanaka
handle fp128 returns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05[mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floatingAkira Hatanaka
point registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176521 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05[mips] Correct handling of fp128 (long double) formals and read long doubleAkira Hatanaka
parameters from floating point registers if target is mips64 hard float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05reverting patch 176508.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Add support for lowering block address.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Fixes a test by replacing .align by .p2align and setting triples explicitly.Eli Bendersky
Patch by David Sehr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176502 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Hexagon: Add encoding bits to the TFR64 instructions.Jyotsna Verma
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05Add a test that .align directives on capable processors use long NOPs.David Sehr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: Turn BUILD_VECTOR into Reg_SequenceVincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176487 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05R600: Use MUL_IEEE for trig/fdiv intrinsicVincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176485 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit ↵NAKAMURA Takumi
-mtriple=mips64el-unknown-unknown to appease win32. FIXME: Is it expected for win32 to affect mips targets? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown ↵NAKAMURA Takumi
to appease win32 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05The current X86 NOP padding uses one long NOP followed by the remainder inDavid Sehr
one-byte NOPs. If the processor actually executes those NOPs, as it sometimes does with aligned bundling, this can have a performance impact. From my micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch changes NOP emission to emit as many 15-byte (the maximum) as possible followed by at most one shorter NOP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Check isDiscardableIfUnused, rather than hasLocalLinkage, when bumpingLang Hames
GlobalValue linkage up to ExternalLinkage in the ExtractGV pass. This prevents linkonce and linkonce_odr symbols from being DCE'd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04[mips] Print move instructions.Akira Hatanaka
"move $4, $5" is printed instead of "or $4, $5, $zero". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Mips specific inline assembler constraint 'R'Jack Carter
'R' An address that can be sued in a non-macro load or store. This patch includes a positive test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Reapply r176381, writing the CHECKs in a more forgiving manner to account forEli Bendersky
running llvm-objdump on Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04Bypass Slow DividesPreston Gurd
* Only apply divide bypass optimization when not optimizing for size. * Fixed bug caused by constant for 0 value of type Int32, used dividend type to generate the constant instead. * For atom x86-64 apply the divide bypass to use 16-bit divides instead of 64-bit divides when operand values are small enough. * Added lit tests for 64-bit divide bypass. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02ARM: Creating a vector from a lane of another.Jim Grosbach
The VDUP instruction source register doesn't allow a non-constant lane index, so make sure we don't construct a ARM::VDUPLANE node asking it to do so. rdar://13328063 http://llvm.org/bugs/show_bug.cgi?id=13963 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02ARM NEON: Fix v2f32 float intrinsicsArnold Schwaighofer
Mark them as expand, they are not legal as our backend does not match them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02recommit r172363 & r171325 (reverted in r172756)Nuno Lopes
This adds minimalistic support for PHI nodes to llvm.objectsize() evaluation fingers crossed so that it does break clang boostrap again.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02X86 cost model: Adjust cost for custom lowered vector multipliesArnold Schwaighofer
This matters for example in following matrix multiply: int **mmult(int rows, int cols, int **m1, int **m2, int **m3) { int i, j, k, val; for (i=0; i<rows; i++) { for (j=0; j<cols; j++) { val = 0; for (k=0; k<cols; k++) { val += m1[i][k] * m2[k][j]; } m3[i][j] = val; } } return(m3); } Taken from the test-suite benchmark Shootout. We estimate the cost of the multiply to be 2 while we generate 9 instructions for it and end up being quite a bit slower than the scalar version (48% on my machine). Also, properly differentiate between avx1 and avx2. On avx-1 we still split the vector into 2 128bits and handle the subvector muls like above with 9 instructions. Only on avx-2 will we have a cost of 9 for v4i64. I changed the test case in test/Transforms/LoopVectorize/X86/avx1.ll to use an add instead of a mul because with a mul we now no longer vectorize. I did verify that the mul would be indeed more expensive when vectorized with 3 kernels: for (i ...) r += a[i] * 3; for (i ...) m1[i] = m1[i] * 3; // This matches the test case in avx1.ll and a matrix multiply. In each case the vectorized version was considerably slower. radar://13304919 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02PR14448 - prevent the loop vectorizer from vectorizing the same loop twice.Nadav Rotem
The LoopVectorizer often runs multiple times on the same function due to inlining. When this happens the loop vectorizer often vectorizes the same loops multiple times, increasing code size and adding unneeded branches. With this patch, the vectorizer during vectorization puts metadata on scalar loops and marks them as 'already vectorized' so that it knows to ignore them when it sees them a second time. PR14448. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-02Revert "Rewrite a test to count emitted instructions without using -stats"Michael Gottesman
This reverts commit aac7922b8fe7ae733d3fe6697e6789fd730315dc. I am reverting the commit since it broke the phase 1 public buildbot for a few hours. http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RA/builds/2137 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01[mips] Fix inefficient code generation.Akira Hatanaka
This patch eliminates the need to emit a constant move instruction when this pattern is matched: (select (setgt a, Constant), T, F) The pattern above effectively turns into this: (conditional-move (setlt a, Constant + 1), F, T) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176384 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Rewrite a test to count emitted instructions without using -statsEli Bendersky
Also removed the comments of "should produce..." because they completely don't match the actually produced output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176381 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Set properties for f128 type.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176378 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Rewrite a test to check actual output rather than intermediate implementationEli Bendersky
detail. The was this test was written, it was relying on an implementation detail (fixups) and hence was very brittle (relying, among other things, on the exact ordering of statistics printed by MC). The test was rewritten to check a more observable output difference. While it doesn't cover 100% of the things the original test covered, it's a good practice to write regression tests this way. If we want to check that internal details and invariants hold, such tests should be expressed as unit tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176377 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01No need to force-create clang-tools-extra lit.site.cfgEdwin Vane
The make (all) target takes care of creating lit configs and auto-generating tests. The problem with the original 'lit.site.cfg' target is it's not recursive and doesn't fully create everything necessary for testing clang-tools-extra. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176374 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Add regression tests (WORKSFORME)Michael Liao
- These tests wont't crash on trunk but would be better to add them so that they don't break again in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Generate an error message instead of asserting or segfaulting when we can'tChad Rosier
handle indirect register inputs. rdar://13322011 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176367 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01LoopVectorize: Don't hang forever if a PHI only has skipped PHI uses.Benjamin Kramer
Fixes PR15384. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Fix PR10475Michael Liao
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Add support for using non-pic code for arm and thumb1 when emitting the sjljChad Rosier
dispatch code. As far as I can tell the thumb2 code is behaving as expected. I was able to compile and run the associated test case for both arm and thumb1. rdar://13066352 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01R600/SI: fix sampler tests after fixing wait insertionsChristian Konig
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176359 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Hexagon: Add constant extender support framework.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01[mips] Remove unused option. Fix 80-column violations.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01[mips] Add the capability to search delay slot filling instructions inAkira Hatanaka
successor basic blocks. Currently this is off by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176329 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01[mips] Add capability to search in the forward direction for instructions thatAkira Hatanaka
can fill the delay slot. Currently, this is off by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01[mips] Define class MemDefsUses.Akira Hatanaka
This class tracks dependence between memory instructions using underlying objects of memory operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176313 91177308-0d34-0410-b5e6-96231b3b80d8
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